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| www..com User's Manual 78K0/FC2 8-Bit Single-Chip Microcontrollers PD78F0881(A) PD78F0882(A) PD78F0883(A) PD78F0884(A) PD78F0885(A) PD78F0886(A) The 78K0/FC2 has an on-chip debug function. PD78F0881(A2) PD78F0882(A2) PD78F0883(A2) PD78F0884(A2) PD78F0885(A2) PD78F0886(A2) Do not use this product for mass production after the on-chip debug function has been used because its reliability cannot be guaranteed, due to issues with respect to the number of times the flash memory can be rewritten. NEC Electronics does not accept complaints concerning when use this product for mass production after the on-chip debug function has been used. Document No. U17555EJ3V0UD00 (3rd edition) Date Published October 2006 NS CP(K) 2005 Printed in Japan www..com [MEMO] 2 User's Manual U17555EJ3V0UD www..com NOTES FOR CMOS DEVICES 1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN). 2 HANDLING OF UNUSED INPUT PINS Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device. 3 PRECAUTION AGAINST ESD A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices. 4 STATUS BEFORE INITIALIZATION Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions. 5 POWER ON/OFF SEQUENCE In the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. When switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. Use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. The correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. 6 INPUT OF SIGNAL DURING POWER OFF STATE Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. User's Manual U17555EJ3V0UD 3 www..com EEPROM is trademark of NEC Electronics Corporation. Windows, Windows NT and Windows XP are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. PC/AT is a trademark of International Business Machines Corporation. HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. Solaris and SunOS are trademarks of Sun Microsystems, Inc. SuperFlash is a registered trademark of Silicon Storage Technology, Inc. in several countries including the United States and Japan. Caution: This product uses SuperFlash(R) technology licensed from Silicon Storage Technology, inc. * The information in this document is current as of October, 2006. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document. * NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC Electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. * NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to NEC Electronics products developed based on a customerdesignated "quality assurance program" for a specific application. The recommended applications of an NEC Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC Electronics product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to determine NEC Electronics' willingness to support a given application. (Note) (1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its majority-owned subsidiaries. (2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above). M8E 02. 11-1 4 User's Manual U17555EJ3V0UD www..com [MEMO] User's Manual U17555EJ3V0UD 5 www..com INTRODUCTION Readers This manual is intended for user engineers who wish to understand the functions of the 78K0/FC2 and design and develop application systems and programs for these devices. The target products are as follows. 78K0/FC2: PD78F0881 (A), 78F0882 (A), 78F0883 (A), 78F0884 (A), 78F0885 (A), 78F0886 (A), 78F0881 (A2), 78F0882 (A2), 78F0883 (A2), 78F0884 (A2), 78F0885 (A2), 78F0886 (A2) Purpose This manual is intended to give users an understanding of the functions described in the Organization below. The 78K0/FC2 manual is separated into two parts: this manual and the instructions edition (common to the 78K/0 Series). 78K0/FC2 User's Manual (This Manual) * * * * * How to Read This Manual Pin functions Internal block functions Interrupts Other on-chip peripheral functions Electrical specifications 78K/0 Series User's Manual Instructions * CPU functions * Instruction set * Explanation of each instruction Organization It is assumed that the readers of this manual have general knowledge of electrical engineering, logic circuits, and microcontrollers. * When using this manual as the manual for (A) and (A2) grade products: Only the quality grade differs between (A) grade products and (A2) grade products. Read the part number as follows. * PD78F0881 PD78F0881 (A), 78F0881 (A2) * PD78F0882 PD78F0882 (A), 78F0882 (A2) * PD78F0883 PD78F0883 (A), 78F0883 (A2) * PD78F0884 PD78F0894 (A), 78F0894 (A2) * PD78F0885 PD78F0885 (A), 78F0885 (A2) * PD78F0886 PD78F0886 (A), 78F0886 (A2) * To gain a general understanding of functions: Read this manual in the order of the CONTENTS. The mark Conventions Data significance: Active low representations: Note: Caution: Remark: Numerical representations: Higher digits on the left and lower digits on the right xxx (overscore over pin and signal name) Footnote for item marked with Note in the text. Information requiring particular attention Supplementary information ... xxxx or xxxxB Binary ... xxxx Decimal Hexadecimal ... xxxxH 6 User's Manual U17555EJ3V0UD www..com Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents Related to Devices Document Name 78K0/FC2 User's Manual 78K/0 Series Instructions User's Manual Document No. This manual U12326E Documents Related to Development Tools (Software) (User's Manuals) Document Name RA78K0 Ver.3.80 Assembler Package Operation Language Structured Assembly Language CC78K0 Ver.3.70 C Compiler Operation Language ID78K Series Ver. 2.90 or Later Integrated Debugger Project Manager Ver. 5.20 or Later (Windows Based) Operation (Windows(R) Based) Document No. U17199E U17198E U17197E U17201E U17200E U17437E U16934E Documents Related to Development Tools (Hardware) (User's Manuals) Document Name QB-78K0FX2 In-Circuit Emulator QB-78K0MINI ON-CHIP DEBUG Emulator Document No. U17534E U17029E Documents Related to Flash Memory Programming Document Name PG-FP4 Flash Memory Programmer User's Manual Document No. U15260E U17544E PG-FP3 Flash Memory Programmer User's Manual Other Documents Document Name SEMICONDUCTOR SELECTION GUIDE - Products and Packages - Semiconductor Device Mount Manual Quality Grades on NEC Semiconductor Devices NEC Semiconductor Device Reliability/Quality Control System Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) Document No. X13769X Note C11531E C10983E C11892E Note See the "Semiconductor Device Mount Manual" website (http://www.necel.com/pkg/en/mount/index.html). Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document when designing. User's Manual U17555EJ3V0UD 7 www..com CONTENTS CHAPTER 1 OUTLINE ............................................................................................................................ 17 1.1 Features......................................................................................................................................... 17 1.2 Applications .................................................................................................................................. 18 1.3 Ordering Information ................................................................................................................... 18 1.4 Pin Configuration (Top View) ...................................................................................................... 19 1.5 Fx2 Series Lineup......................................................................................................................... 22 1.5.1 78K0/Fx2 product lineup ................................................................................................................... 22 1.6 Block Diagram .............................................................................................................................. 24 1.7 Outline of Functions .................................................................................................................... 26 CHAPTER 2 PIN FUNCTIONS ............................................................................................................... 28 2.1 Pin Function List .......................................................................................................................... 28 2.2 Description of Pin Functions ...................................................................................................... 32 2.2.1 P00, P01, P06 (port 0)....................................................................................................................... 32 2.2.2 P10 to P17 (port 1) ............................................................................................................................ 33 2.2.3 P30 to P33 (port 3) ............................................................................................................................ 34 2.2.4 P40, P41 (port 4) ............................................................................................................................... 34 2.2.5 P60 to P63 (port 6) ............................................................................................................................ 34 2.2.6 P70 to P73 (port 7) ............................................................................................................................ 35 2.2.7 P80 to P87 (port 8) ............................................................................................................................ 35 2.2.8 P90 (port 9) ....................................................................................................................................... 36 2.2.9 P120 to P124 (port 12) ...................................................................................................................... 36 2.2.10 P130, P131 (port 13) ....................................................................................................................... 37 2.2.11 AVREF............................................................................................................................................... 37 2.2.12 AVSS ................................................................................................................................................ 37 2.2.13 RESET ............................................................................................................................................ 37 2.2.14 REGC.............................................................................................................................................. 37 2.2.15 VDD and EVDD .................................................................................................................................. 37 2.2.16 VSS and EVSS................................................................................................................................... 37 2.2.17 FLMD0 ............................................................................................................................................ 38 2.3 Pin I/O Circuits and Recommended Connection of Unused Pins ........................................... 39 CHAPTER 3 CPU ARCHITECTURE ...................................................................................................... 43 3.1 Memory Space .............................................................................................................................. 43 3.1.1 Internal program memory space........................................................................................................ 48 3.1.2 Internal data memory space .............................................................................................................. 49 3.1.3 Special function register (SFR) area ................................................................................................. 49 3.1.4 Data memory addressing .................................................................................................................. 50 3.2 Processor Registers .................................................................................................................... 54 3.2.1 Control registers ................................................................................................................................ 54 3.2.2 General-purpose registers................................................................................................................. 58 3.2.3 Special Function Registers (SFRs) ................................................................................................... 59 3.3 Instruction Address Addressing................................................................................................. 65 3.3.1 Relative addressing........................................................................................................................... 65 3.3.2 Immediate addressing ....................................................................................................................... 66 8 User's Manual U17555EJ3V0UD www..com 3.3.3 Table indirect addressing ...................................................................................................................67 3.3.4 Register addressing ...........................................................................................................................67 3.4 Operand Address Addressing .................................................................................................... 68 3.4.1 Implied addressing .............................................................................................................................68 3.4.2 Register addressing ...........................................................................................................................69 3.4.3 Direct addressing ...............................................................................................................................70 3.4.4 Short direct addressing ......................................................................................................................71 3.4.5 Special function register (SFR) addressing........................................................................................72 3.4.6 Register indirect addressing...............................................................................................................73 3.4.7 Based addressing ..............................................................................................................................74 3.4.8 Based indexed addressing.................................................................................................................75 3.4.9 Stack addressing................................................................................................................................76 CHAPTER 4 PORT FUNCTIONS........................................................................................................... 77 4.1 Port Functions .............................................................................................................................. 77 4.2 Port Configuration ....................................................................................................................... 78 4.2.1 Port 0 .................................................................................................................................................79 4.2.2 Port 1 .................................................................................................................................................81 4.2.3 Port 3 .................................................................................................................................................84 4.2.4 Port 4 .................................................................................................................................................86 4.2.5 Port 6 .................................................................................................................................................87 4.2.6 Port 7 .................................................................................................................................................88 4.2.7 Port 8 .................................................................................................................................................91 4.2.8 Port 9 .................................................................................................................................................92 4.2.9 Port 12 ...............................................................................................................................................94 4.2.10 Port 13 .............................................................................................................................................97 4.3 Registers Controlling Port Function .......................................................................................... 99 4.4 Port Function Operations.......................................................................................................... 106 4.4.1 Writing to I/O port .............................................................................................................................106 4.4.2 Reading from I/O port.......................................................................................................................106 4.4.3 Operations on I/O port......................................................................................................................106 4.5 Cautions on 1-Bit Manipulation Instruction for Port Register n (Pn).................................... 107 CHAPTER 5 CLOCK GENERATOR .................................................................................................... 108 5.1 Functions of Clock Generator................................................................................................... 108 5.2 Configuration of Clock Generator ............................................................................................ 109 5.3 Registers Controlling Clock Generator ................................................................................... 111 5.4 System Clock Oscillator ............................................................................................................ 120 5.4.1 X1 oscillator .....................................................................................................................................120 5.4.2 XT1 oscillator ...................................................................................................................................120 5.4.3 When subsystem clock is not used ..................................................................................................123 5.4.4 Internal high-speed oscillator ...........................................................................................................123 5.4.5 Internal low-speed oscillator.............................................................................................................123 5.4.6 Prescaler..........................................................................................................................................123 5.5 Clock Generator Operation ....................................................................................................... 124 5.6 Controlling Clock ....................................................................................................................... 128 5.6.1 Controlling high-speed system clock................................................................................................128 5.6.2 Example of controlling internal high-speed oscillation clock.............................................................131 User's Manual U17555EJ3V0UD 9 www..com 5.6.3 Example of controlling subsystem clock...........................................................................................133 5.6.4 Controlling internal low-speed oscillation clock ................................................................................135 5.6.5 Clocks supplied to CPU and peripheral hardware ............................................................................135 5.6.6 CPU clock status transition diagram.................................................................................................136 5.6.7 Condition before changing CPU clock and processing after changing CPU clock ...........................141 5.6.8 Time required for switchover of CPU clock and main system clock .................................................142 5.6.9 Conditions before clock oscillation is stopped ..................................................................................143 CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01......................................................... 144 6.1 Functions of 16-Bit Timer/Event Counters 00 and 01............................................................. 145 6.2 Configuration of 16-Bit Timer/Event Counters 00 and 01 ...................................................... 146 6.3 Registers Controlling 16-Bit Timer/Event Counters 00 and 01.............................................. 154 6.4 Operation of 16-Bit Timer/Event Counters 00 and 01 ............................................................. 166 6.4.1 Interval timer operation.....................................................................................................................166 6.4.2 PPG output operations .....................................................................................................................169 6.4.3 Pulse width measurement operations ..............................................................................................172 6.4.4 External event counter operation......................................................................................................180 6.4.5 Square-wave output operation .........................................................................................................183 6.4.6 One-shot pulse output operation ......................................................................................................185 6.5 Special Use of TM0n .................................................................................................................. 190 6.5.1 Rewriting CR01n during TM0n operation .........................................................................................190 6.5.2 Setting LVS0n and LVR0n ...............................................................................................................190 6.6 Cautions for 16-Bit Timer/Event Counters 00 and 01 ............................................................. 192 CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51........................................................... 196 7.1 Functions of 8-Bit Timer/Event Counters 50 and 51............................................................... 196 7.2 Configuration of 8-Bit Timer/Event Counters 50 and 51 ........................................................ 198 7.3 Registers Controlling 8-Bit Timer/Event Counters 50 and 51................................................ 200 7.4 Operations of 8-Bit Timer/Event Counters 50 and 51 ............................................................. 205 7.4.1 Operation as interval timer ...............................................................................................................205 7.4.2 Operation as external event counter ................................................................................................207 7.4.3 Square-wave output operation .........................................................................................................208 7.4.4 PWM output operation......................................................................................................................209 7.5 Cautions for 8-Bit Timer/Event Counters 50 and 51 ............................................................... 213 CHAPTER 8 8-BIT TIMERS H0 AND H1 .......................................................................................... 214 8.1 Functions of 8-Bit Timers H0 and H1 ....................................................................................... 214 8.2 Configuration of 8-Bit Timers H0 and H1................................................................................. 214 8.3 Registers Controlling 8-Bit Timers H0 and H1 ........................................................................ 218 8.4 Operation of 8-Bit Timers H0 and H1........................................................................................ 223 8.4.1 Operation as interval timer/square-wave output ...............................................................................223 8.4.2 Operation as PWM output mode ......................................................................................................226 8.4.3 Carrier generator mode operation (8-bit timer H1 only)....................................................................232 CHAPTER 9 WATCH TIMER................................................................................................................ 239 9.1 Functions of Watch Timer ......................................................................................................... 239 9.2 Configuration of Watch Timer................................................................................................... 240 9.3 Register Controlling Watch Timer ............................................................................................ 241 10 User's Manual U17555EJ3V0UD www..com 9.4 Watch Timer Operations............................................................................................................ 243 9.4.1 Watch timer operation ......................................................................................................................243 9.4.2 Interval timer operation ....................................................................................................................244 9.5 Cautions for Watch Timer ......................................................................................................... 245 CHAPTER 10 WATCHDOG TIMER ..................................................................................................... 246 10.1 Functions of Watchdog Timer ................................................................................................ 246 10.2 Configuration of Watchdog Timer.......................................................................................... 247 10.3 Register Controlling Watchdog Timer ................................................................................... 248 10.4 Operation of Watchdog Timer................................................................................................. 249 10.4.1 Controlling operation of watchdog timer.........................................................................................249 10.4.2 Setting overflow time of watchdog timer.........................................................................................251 10.4.3 Setting window open period of watchdog timer ..............................................................................252 CHAPTER 11 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER............................................... 254 11.1 Functions of Clock Output/Buzzer Output Controller.......................................................... 254 11.2 Configuration of Clock Output/Buzzer Output Controller ................................................... 255 11.3 Register Controlling Clock Output/Buzzer Output Controller............................................. 255 11.4 Clock Output/Buzzer Output Controller Operations............................................................. 258 11.4.1 Clock output operation ...................................................................................................................258 11.4.2 Operation as buzzer output ............................................................................................................258 CHAPTER 12 A/D CONVERTER ......................................................................................................... 259 12.1 Function of A/D Converter ...................................................................................................... 259 12.2 Configuration of A/D Converter .............................................................................................. 260 12.3 Registers Used in A/D Converter ........................................................................................... 262 12.4 A/D Converter Operations ....................................................................................................... 271 12.4.1 Basic operations of A/D converter..................................................................................................271 12.4.2 Input voltage and conversion results..............................................................................................273 12.4.3 A/D converter operation mode .......................................................................................................274 12.5 How to Read A/D Converter Characteristics Table .............................................................. 276 12.6 Cautions for A/D Converter..................................................................................................... 278 CHAPTER 13 SERIAL INTERFACES UART60 AND UART61.......................................................... 282 13.1 Functions of Serial Interfaces UART60 and UART61 ........................................................... 282 13.2 Configurations of Serial Interface UART60 and UART61..................................................... 287 13.3 Registers Controlling Serial Interfaces UART60 and UART61 ............................................ 291 13.4 Operations of Serial Interface UART60 and UART61 ........................................................... 310 13.4.1 Operation stop mode......................................................................................................................310 13.4.2 Asynchronous serial interface (UART) mode .................................................................................311 13.4.3 Dedicated baud rate generator ......................................................................................................326 CHAPTER 14 SERIAL INTERFACE CSI10 ........................................................................................ 332 14.1 Functions of Serial Interface CSI10........................................................................................ 332 14.2 Configuration of Serial Interface CSI10 ................................................................................. 333 14.3 Registers Controlling Serial Interface CSI10......................................................................... 335 14.4 Operation of Serial Interface CSI10........................................................................................ 338 14.4.1 Operation stop mode......................................................................................................................338 User's Manual U17555EJ3V0UD 11 www..com 14.4.2 3-wire serial I/O mode ....................................................................................................................339 CHAPTER 15 CAN CONTROLLER ..................................................................................................... 349 15.1 Outline Description .................................................................................................................. 349 15.1.1 Features .........................................................................................................................................349 15.1.2 Overview of functions .....................................................................................................................350 15.1.3 Configuration ..................................................................................................................................351 15.2 CAN Protocol ............................................................................................................................ 352 15.2.1 Frame format..................................................................................................................................352 15.2.2 Frame types ...................................................................................................................................353 15.2.3 Data frame and remote frame ........................................................................................................353 15.2.4 Error frame .....................................................................................................................................361 15.2.5 Overload frame...............................................................................................................................362 15.3 Functions .................................................................................................................................. 363 15.3.1 Determining bus priority .................................................................................................................363 15.3.2 Bit stuffing ......................................................................................................................................363 15.3.3 Multi masters ..................................................................................................................................363 15.3.4 Multi cast ........................................................................................................................................363 15.3.5 CAN sleep mode/CAN stop mode function ....................................................................................363 15.3.6 Error control function ......................................................................................................................364 15.3.7 Baud rate control function ..............................................................................................................370 15.4 Connection With Target System ............................................................................................. 374 15.5 Internal Registers Of CAN Controller ..................................................................................... 375 15.5.1 CAN controller configuration...........................................................................................................375 15.5.2 Register access type ......................................................................................................................376 15.5.3 Register bit configuration................................................................................................................385 15.6 Bit Set/Clear Function.............................................................................................................. 389 15.7 Control Registers ..................................................................................................................... 391 15.8 CAN Controller Initialization.................................................................................................... 426 15.8.1 Initialization of CAN module ...........................................................................................................426 15.8.2 Initialization of message buffer .......................................................................................................426 15.8.3 Redefinition of message buffer.......................................................................................................426 15.8.4 Transition from initialization mode to operation mode ....................................................................427 15.8.5 Resetting error counter C0ERC of CAN module ............................................................................428 15.9 Message Reception .................................................................................................................. 429 15.9.1 Message reception .........................................................................................................................429 15.9.2 Receive Data Read ........................................................................................................................430 15.9.3 Receive history list function ............................................................................................................431 15.9.4 Mask function .................................................................................................................................433 15.9.5 Multi buffer receive block function ..................................................................................................435 15.9.6 Remote frame reception .................................................................................................................436 15.10 Message Transmission.......................................................................................................... 437 15.10.1 Message transmission..................................................................................................................437 15.10.2 Transmit history list function .........................................................................................................439 15.10.3 Automatic block transmission (ABT).............................................................................................441 15.10.4 Transmission abort process .........................................................................................................442 15.10.5 Remote frame transmission..........................................................................................................443 15.11 Power Save Modes................................................................................................................. 444 12 User's Manual U17555EJ3V0UD www..com 15.11.1 CAN sleep mode ..........................................................................................................................444 15.11.2 CAN stop mode............................................................................................................................446 15.11.3 Example of using power saving modes........................................................................................447 15.12 Interrupt Function .................................................................................................................. 448 15.13 Diagnosis Functions And Special Operational Modes ...................................................... 449 15.13.1 Receive-only mode ......................................................................................................................449 15.13.2 Single-shot mode .........................................................................................................................450 15.13.3 Self-test mode ..............................................................................................................................451 15.13.4 Receive/Transmit Operation in Each Operation Mode .................................................................452 15.14 Time Stamp Function............................................................................................................. 453 15.14.1 Time stamp function.....................................................................................................................453 15.15 Baud Rate Settings ................................................................................................................ 455 15.15.1 Baud rate settings ........................................................................................................................455 15.15.2 Representative examples of baud rate settings ...........................................................................459 15.16 Operation Of CAN Controller ................................................................................................ 463 CHAPTER 16 INTERRUPT FUNCTIONS ............................................................................................ 489 16.1 Interrupt Function Types......................................................................................................... 489 16.2 Interrupt Sources and Configuration ..................................................................................... 489 16.3 Registers Controlling Interrupt Functions ............................................................................ 493 16.4 Interrupt Servicing Operations ............................................................................................... 501 16.4.1 Maskable interrupt acknowledgement............................................................................................501 16.4.2 Software interrupt request acknowledgement ................................................................................503 16.4.3 Multiple interrupt servicing .............................................................................................................504 16.4.4 Interrupt request hold .....................................................................................................................507 CHAPTER 17 STANDBY FUNCTION.................................................................................................. 508 17.1 Standby Function and Configuration..................................................................................... 508 17.1.1 Standby function ............................................................................................................................508 17.1.2 Registers controlling standby function............................................................................................508 17.2 Standby Function Operation................................................................................................... 511 17.2.1 HALT mode ....................................................................................................................................511 17.2.2 STOP mode ...................................................................................................................................516 CHAPTER 18 RESET FUNCTION ....................................................................................................... 523 18.1 Register for Confirming Reset Source................................................................................... 531 CHAPTER 19 MULTIPLIER/DIVIDER................................................................................................... 532 19.1 Functions of Multiplier/Divider ............................................................................................... 532 19.2 Configuration of Multiplier/Divider......................................................................................... 532 19.3 Register Controlling Multiplier/Divider .................................................................................. 536 19.4 Operations of Multiplier/Divider.............................................................................................. 537 19.4.1 Multiplication operation ..................................................................................................................537 19.4.2 Division operation...........................................................................................................................539 CHAPTER 20 POWER-ON-CLEAR CIRCUIT ..................................................................................... 541 20.1 Functions of Power-on-Clear Circuit ..................................................................................... 541 20.2 Configuration of Power-on-Clear Circuit ............................................................................... 542 User's Manual U17555EJ3V0UD 13 www..com 20.3 Operation of Power-on-Clear Circuit ...................................................................................... 542 20.4 Cautions for Power-on-Clear Circuit ...................................................................................... 545 CHAPTER 21 LOW-VOLTAGE DETECTOR ....................................................................................... 547 21.1 Functions of Low-Voltage Detector........................................................................................ 547 21.2 Configuration of Low-Voltage Detector ................................................................................. 548 21.3 Registers Controlling Low-Voltage Detector......................................................................... 548 21.4 Operation of Low-Voltage Detector ........................................................................................ 551 21.4.1 When used as reset .......................................................................................................................552 21.4.2 When used as interrupt ..................................................................................................................557 21.5 Cautions for Low-Voltage Detector ........................................................................................ 562 CHAPTER 22 OPTION BYTE............................................................................................................... 565 22.1 Functions of Option Bytes ...................................................................................................... 565 22.2 Format of Option Byte ............................................................................................................. 567 CHAPTER 23 FLASH MEMORY .......................................................................................................... 570 23.1 Internal Memory Size Switching Register.............................................................................. 570 23.2 Internal Expansion RAM Size Switching Register ................................................................ 571 23.3 Writing with Flash Memory Programmer ............................................................................... 572 23.4 Programming Environment ..................................................................................................... 578 23.5 Communication Mode.............................................................................................................. 578 23.6 Connection of Pins on Board.................................................................................................. 580 23.6.1 FLMD0 pin......................................................................................................................................580 23.6.2 Serial interface pins........................................................................................................................580 23.6.3 RESET pin......................................................................................................................................582 23.6.4 Port pins .........................................................................................................................................582 23.6.5 REGC pin .......................................................................................................................................582 23.6.6 Other signal pins ............................................................................................................................582 23.6.7 Power supply..................................................................................................................................583 23.7 Programming Method .............................................................................................................. 584 23.7.1 Controlling flash memory................................................................................................................584 23.7.2 Flash memory programming mode.................................................................................................584 23.7.3 Selecting communication mode......................................................................................................585 23.7.4 Communication commands ............................................................................................................586 23.8 Security Settings ...................................................................................................................... 587 23.9 Processing Time for Each Command When PG-FP4 Is Used (Reference)......................... 589 23.10 Flash Memory Programming by Self-Programming ........................................................... 590 23.10.1 Registers used for self-programming function ..............................................................................596 23.11 Boot swap function ................................................................................................................ 600 CHAPTER 24 ON-CHIP DEBUG FUNCTION ..................................................................................... 602 24.1 Outline of Functions ................................................................................................................ 602 24.2 Connection with MINICUBE..................................................................................................... 603 24.3 Connection Circuit Examples ................................................................................................. 604 24.4 On-Chip Debug Security ID ..................................................................................................... 606 24.5 Restrictions and Cautions on On-Chip Debug Function ..................................................... 606 14 User's Manual U17555EJ3V0UD www..com CHAPTER 25 INSTRUCTION SET ...................................................................................................... 607 25.1 Conventions Used in Operation List...................................................................................... 607 25.1.1 Operand identifiers and specification methods ..............................................................................607 25.1.2 Description of operation column.....................................................................................................608 25.1.3 Description of flag operation column ..............................................................................................608 25.2 Operation List ........................................................................................................................... 609 25.3 Instructions Listed by Addressing Type ............................................................................... 617 CHAPTER 26 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS).................................. 620 26.1 Absolute Maximum Ratings .................................................................................................... 620 26.2 Oscillator Characteristics........................................................................................................ 622 26.3 DC Characteristics ................................................................................................................... 624 27.4 AC Characteristics ................................................................................................................... 631 27.5 Data Retention Characteristics............................................................................................... 641 27.6 Flash EEPROM Programming Characteristics...................................................................... 642 CHAPTER 27 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS)................................ 643 27.1 Absolute Maximum Ratings .................................................................................................... 643 27.2 Oscillator Characteristics........................................................................................................ 645 27.3 DC Characteristics ................................................................................................................... 647 27.4 AC Characteristics ................................................................................................................... 653 27.5 Data Retention Characteristics............................................................................................... 663 27.6 Flash EEPROM Programming Characteristics...................................................................... 664 CHAPTER 28 PACKAGE DRAWINGS................................................................................................ 665 CHAPTER 29 RECOMMENDED SOLDERING CONDITIONS........................................................... 667 CHAPTER 30 CAUTIONS FOR WAIT ................................................................................................ 668 30.1 Cautions for Wait ..................................................................................................................... 668 30.2 Peripheral Hardware That Generates Wait ............................................................................ 669 30.3 Example of Wait Occurrence .................................................................................................. 671 APPENDIX A DEVELOPMENT TOOLS .............................................................................................. 672 A.1 Software Package...................................................................................................................... 676 A.2 Language Processing Software............................................................................................... 676 A.3 Control Software........................................................................................................................ 677 A.4 Flash Memory Programming Tools ......................................................................................... 678 A.4.1 When using flash memory programmer FG-FP4, FL-PR4, PG-FPL3, and FP-LITE3......................678 A.4.2 When using on-chip debug emulator with programming function QB-MINI2 ...................................678 A.5 Debugging Tools (Hardware) ................................................................................................... 679 A.5.1 When using in-circuit emulator QB-78K0FX2 ..................................................................................679 A.5.2 When using on-chip debug emulator QB-78K0MINI ........................................................................679 A.5.3 When using on-chip debug emulator with programming function QB-MINI2 ...................................680 A.6 Debugging Tools (Software)..................................................................................................... 680 User's Manual U17555EJ3V0UD 15 www..com APPENDIX B NOTES ON TARGET SYSTEM DESIGN ................................................................... 681 APPENDIX C REGISTER INDEX ......................................................................................................... 683 C.1 Register Index (In Alphabetical Order with Respect to Register Names) ............................ 683 C.2 Register Index (In Alphabetical Order with Respect to Register Symbol)........................... 688 APPENDIX D REVISION HISTORY ..................................................................................................... 692 D.1 Main Revisions in this Edition.................................................................................................. 692 D.2 Revision History of Preceding Editions .................................................................................. 702 16 User's Manual U17555EJ3V0UD www..com CHAPTER 1 OUTLINE 1.1 Features Minimum instruction execution time can be changed from high speed (0.1 s: @ 20 MHz operation with highspeed system clock) to ultra low-speed (122 s: @ 32.768 kHz operation with subsystem clock) General-purpose register: 8 bits x 32 registers (8 bits x 8 registers x 4 banks) ROM, RAM capacities Item Part Number Program Memory (ROM) Flash memory Note Data Memory Internal High-Speed RAM Note Internal Expansion RAM 1024 bytes 2048 bytes Note PD78F0881, 78F0884 PD78F0882, 78F0885 PD78F0883, 78F0886 32 KB 48 KB 60 KB 1024 bytes Note The internal flash memory, internal high-speed RAM capacities, and internal expansion RAM capacities can be changed using the internal memory size switching register (IMS) and the internal expansion RAM size switching register (IXS). On-chip single-power-supply flash memory Self-programming (with boot swap function) On-chip debug function On-chip power-on-clear (POC) circuit and low-voltage detector (LVI) Short startup is possible via the CPU default start using the on-chip internal high-speed oscillator On-chip watchdog timer (operable with on-chip internal low-speed oscillator clock) On-chip multiplier/divider On-chip clock output/buzzer output controller I/O ports: PD78F0881, 78F0882, 78F0883: 37 (N-ch open drain: 3) PD78F0884, 78F0885, 78F0886: 41 (N-ch open drain: 4) Timer: 8 channels Note 1 Serial interface: 3 channels (UART (LIN (Local Interconnect Network)-bus supported): 1 channel, CSI/UART Note 2: 1 channel, CAN: 1 channel) 10-bit resolution A/D converter: PD78F0881, 78F0882, 78F0883: 8 channels PD78F0884, 78F0885, 78F0886: 9 channels Supply voltage: VDD = 4.0 to 5.5 V when 20 MHz, VDD = 2.7 to 5.5 V when 10 MHz, VDD = 1.8 to 5.5 V when 5 MHz (with internal high-speed oscillator clock or subsystem clock: VDD = 1.8 to 5.5 V) Operating ambient temperature: TA = -40 to +85C, -40 to +125C Notes 1. Since TM01 does not have the following terminal at 78K0/FC2, the function is restricted in part. PD78F0881, 78F0882, and 78F0883: TI001, TI011, TO01 PD78F0884, 78F0885, and 78F0886: TI001 2. Select either of the functions of these alternate-function pins. User's Manual U17555EJ3V0UD 17 www..com CHAPTER 1 OUTLINE 1.2 Applications Automotive electrical appliances (Body control, Door control, Front light control) Industrial equipment (Industrial robot, Building control) 1.3 Ordering Information * Flash memory version Part Number Package 44-pin plastic LQFP (10x10) 44-pin plastic LQFP (10x10) 44-pin plastic LQFP (10x10) 44-pin plastic LQFP (10x10) 44-pin plastic LQFP (10x10) 44-pin plastic LQFP (10x10) 48-pin plastic LQFP (Fine pitch) (7x7) 48-pin plastic LQFP (Fine pitch) (7x7) 48-pin plastic LQFP (Fine pitch) (7x7) 48-pin plastic LQFP (Fine pitch) (7x7) 48-pin plastic LQFP (Fine pitch) (7x7) 48-pin plastic LQFP (Fine pitch) (7x7) Quality Grade Special Special Special Special Special Special Special Special Special Special Special Special PD78F0881GB(A)-GAF-AX PD78F0881GB(A2)-GAF-AX PD78F0882GB(A)-GAF-AX PD78F0882GB(A2)-GAF-AX PD78F0883GB(A)-GAF-AX PD78F0883GB(A2)-GAF-AX PD78F0884GA(A)-GAM-AX PD78F0884GA(A2)-GAM-AX PD78F0885GA(A)-GAM-AX PD78F0885GA(A2)-GAM-AX PD78F0886GA(A)-GAM-AX PD78F0886GA(A2)-GAM-AX Remark All these products are lead free products. 18 User's Manual U17555EJ3V0UD www..com CHAPTER 1 OUTLINE 1.4 Pin Configuration (Top View) * 44-pin plastic LQFP (10x10) P120/INTP0/EXLVI P00/TI000 P01/TI010/TO00 P80/ANI0 P81/ANI1 P82/ANI2 P83/ANI3 P84/ANI4 P85/ANI5 P86/ANI6 P87/ANI7 P41 P40 RESET P124/XT2/EXCLKS P123/XT1 FLMD0 P122/X2/EXCLK P121/X1 REGC VSS/EVSS VDD/EVDD 44 43 42 41 40 39 38 37 36 35 34 1 33 2 32 3 31 4 30 5 29 6 28 7 27 8 26 9 25 10 24 11 23 12 13 14 15 16 17 18 19 20 21 22 AVSS AVREF P10/SCK10/TxD61 P11/SI10/RxD61 P12/SO10 P13/TxD60 P14/RxD60 P15/TOH0 P16/TOH1/INTP5 P17/TI50/TO50 P30/INTP1 Cautions 1. Make AVSS the same potential as VSS/EVSS. 2. Connect the REGC pin to VSS via a capacitor (0.47 to 1 F: recommended). 3. ANI0/P80 to ANI7/P87 are set in the analog input mode after release of reset. P60 P61 P62 P33/TI51/TO51/INTP4 P130 P73/BUZ/INTP7 P72/PCL/INTP6 P71/CRxD P70/CTxD P32/INTP3 P31/INTP2 User's Manual U17555EJ3V0UD 19 www..com CHAPTER 1 OUTLINE * 48-pin plastic LQFP (Fine pitch) (7x7) P131 P00/TI000 P01/TI010/TO00 P80/ANI0 P81/ANI1 P82/ANI2 P83/ANI3 P84/ANI4 P85/ANI5 P86/ANI6 P87/ANI7 P90/ANI8 P120/INTP0/EXLVI P41 P40 RESET P124/XT2/EXCLKS P123/XT1 FLMD0 P122/X2/EXCLK P121/X1 REGC VSS/EVSS VDD/EVDD 1 2 3 4 5 6 7 8 9 10 11 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 12 25 13 14 15 16 17 18 19 20 21 22 23 24 AVSS AVREF P10/SCK10/TxD61 P11/SI10/RxD61 P12/SO10 P13/TxD60 P14/RxD60 P15/TOH0 P16/TOH1/INTP5 P17/TI50/TO50 P30/INTP1 P31/INTP2 Cautions 1. Make AVSS the same potential as VSS/EVSS. 2. Connect the REGC pin to VSS via a capacitor (0.47 to 1 F: recommended). 3. ANI0/P80 to ANI7/P87 are set in the analog input mode after release of reset. 20 P60 P61 P62 P63 P33/TI51/TO51/INTP4 P130 P73/BUZ/INTP7 P72/PCL/INTP6 P71/CRxD P70/CTxD P06/TI011/TO01 P32/INTP3 User's Manual U17555EJ3V0UD www..com CHAPTER 1 OUTLINE Pin Identification User's Manual U17555EJ3V0UD 21 www..com CHAPTER 1 OUTLINE 1.5 Fx2 Series Lineup 1.5.1 78K0/Fx2 product lineup * 44-pin LQFP (10 x 10 mm 0.8 mm pitch) 78K0/FC2 PD78F0881 Single-power-supply flash memory: 32 KB, RAM: 2 KB PD78F0882 Single-power-supply flash memory: 48 KB, RAM: 3 KB PD78F0883 Single-power-supply flash memory: 60KB, RAM: 3 KB * 48-pin LQFP (7 x 7 mm 0.5 mm pitch) 78K0/FC2 PD78F0884 Single-power-supply flash memory: 32 KB, RAM: 2 KB PD78F0885 Single-power-supply flash memory: 48 KB, RAM: 3 KB PD78F0886 Single-power-supply flash memory: 60KB, RAM: 3 KB * 64-pin LQFP (10 x 10 mm 0.5 mm pitch, 12 x 12 mm 0.65 mm pitch) 78K0/FE2 PD78F0887 Single-power-supply flash memory: 48 KB, RAM: 3 KB PD78F0888 Single-power-supply flash memory: 60 KB, RAM: 3 KB PD78F0889 Single-power-supply flash memory: 96 KB, RAM: 5 KB PD78F0890 Single-power-supply flash memory: 128 KB, RAM: 7 KB * 80-pin LQFP (12 x 12 mm 0.5 mm pitch, 14 x 14 mm 0.65 mm pitch) 78K0/FF2 PD78F0891 Single-power-supply flash memory: 60 KB, RAM: 3 KB PD78F0892 Single-power-supply flash memory: 96 KB, RAM: 5 KB PD78F0893 Single-power-supply flash memory: 128 KB, RAM: 7 KB Remark All product with on-chip debug function. 22 User's Manual U17555EJ3V0UD www..com CHAPTER 1 OUTLINE The list of functions in the 78K0/Fx2 is shown below. Part Number Item Number of pins Internal memory (bytes) Flash memory RAM 44 pins 48 pins 64 pins 48 K/60 K/96 K/128 K 3 K/3 K/5 K/7 K 80 pins 60 K/96 K/128 K 3 K/5 K/7 K 32 K/48 K/60 K 2 K/3 K/3 K 78K0/FC2 78K0/FE2 78K0/FF2 Power supply voltage Minimum instruction execution time Clock Crystal/ceramic Subclock Internal low-speed oscillator Internal high-speed oscillator Ports CMOS I/O CMOS output N-ch open-drain I/O Timer 16 bits (TM0) 8 bits (TM5) 8 bits (TMH) For watch WDT Serial CAN interface 3-wire CSI LIN-UART LIN-UART/CSI 3 33 VDD = 4.0 to 5.5 V when 20 MHz, VDD = 2.7 to 5.5 V when 10 MHz, VDD = 1.8 to 5.5 V when 5 MHz 0.1 s (when 20 MHz, VDD = 4.0 to 5.5 V) 4 to 20 MHz 32.768 kHz 240 kHz (TYP.) 8 MHz (TYP., VDD = 2.7 to 5.5 V) 36 50 1 4 2 ch Note 66 4 ch 2 ch 2 ch 1 ch 1 ch 1 ch - 1 ch 1 ch 8 ch 20 Provided 9 ch 12 ch 8 1 ch 10-bit A/D converter Interrupts External Internal Reset RESET pin POC LVI WDT Multiplier/divider Clock output/buzzer output Self-programming function On-chip debug function Standby function Operating ambient temperature 16 ch 21 1.59 V 0.15 V (detection voltage is fixed) 4.24/4.09/3.93/3.78/3.62/3.47/3.32/3.16/3.01/2.85/2.70/2.55/2.39/2.24/2.08/1.93 V (selectable by software) Provided Provided Provided Provided Provided HALT/STOP mode TA = -40 to +85C, -40 to +125C Note Since TM01 does not have the following terminal at 78K0/FC2, the function is restricted in part. PD78F0881, 78F0882, and 78F0883: TI001, TI011, TO01 PD78F0884, 78F0885, and 78F0886: TI001 User's Manual U17555EJ3V0UD 23 www..com CHAPTER 1 OUTLINE 1.6 Block Diagram * PD78F0881, 78F0882, 78F0883 TO00/TI010/P01 TI000/P00 (LINSEL) RxD60/P14 (LINSEL) 16-bit timer/ event counter 00 Port 0 2 P00, P01 Port 1 16-bit timer/ event counter 01 Port 3 8 P10-P17 4 P30-P33 TOH0/P15 8-bit timer H0 Port 4 2 P40, P41 TOH1/P16 8-bit timer H1 Port 6 3 P60-P62 Port 7 TI50/TO50/P17 8-bit timer/ event counter 50 Port 8 TI51/TO51/P33 8-bit timer/ event counter 51 Low-speed internal oscillator Watchdog timer 78K/0 CPU core Bank Port 13 Flash memory 4 P70-P73 8 P80-P87 Port 12 5 P120-P124 P130 Buzzer output BUZ/P73 Watch timer Serial interface UART60 LINSEL Serial interface UART61 RxD60/P14 TxD60/P13 Internal high-speed RAM Internal expansion RAM Clock output control PCL/P72 Multiplier/Divider Power on clear/ low voltage indicator Reset control RxD61/P11 TxD61/P10 SCK10/P10 SI10/P11 SO10/P12 ANI0/P80-ANI7/P87 AVREF AVSS INTP0/P120 (LINSEL) RxD60/P14 (LINSEL) INTP1/P30INTP4/P33 INTP5/P16 INTP6/P72 INTP7/P73 CRxD/P71 CTxD/P70 2 4 8 POC/LVI control EXLVI/P120 Serial interface CSI10 System control A/D converter High-speed internal oscillator RESET X1/P121 X2/EXCLK/P122 XT1/P123 XT2/EXCLKS/P124 VDD, VSS, FLMD0 EVDD EVSS Interrupt control On-chip debugger CAN 24 User's Manual U17555EJ3V0UD www..com CHAPTER 1 OUTLINE * PD78F0884, 78F0885, 78F0886 TO00/TI010/P01 TI000/P00 (LINSEL) RxD60/P14 (LINSEL) TO01/TI011/P06 16-bit timer/ event counter 00 Port 0 3 P00, P01, P06 Port 1 16-bit timer/ event counter 01 Port 3 8 P10-P17 4 P30-P33 TOH0/P15 8-bit timer H0 Port 4 2 P40, P41 TOH1/P16 8-bit timer H1 Port 6 4 P60-P63 Port 7 TI50/TO50/P17 8-bit timer/ event counter 50 Port 8 TI51/TO51/P33 8-bit timer/ event counter 51 Low-speed internal oscillator Watchdog timer 78K/0 CPU core Bank Port 12 Flash memory 4 P70-P73 8 P80-P87 Port 9 P90 5 P120-P124 P130 P131 BUZ/P73 Port 13 Watch timer Serial interface UART60 LINSEL Serial interface UART61 RxD60/P14 TxD60/P13 Internal high-speed RAM Internal expansion RAM Buzzer output Clock output control PCL/P72 RxD61/P11 TxD61/P10 SCK10/P10 SI10/P11 SO10/P12 Multiplier/Divider Power on clear/ low voltage indicator Reset control Serial interface CSI10 POC/LVI control EXLVI/P120 ANI0/P80-ANI7/P87, ANI8/P90 AVREF AVSS INTP0/P120 (LINSEL) RxD60/P14 (LINSEL) INTP1/P30INTP4/P33 INTP5/P16 INTP6/P72 INTP7/P73 CRxD/P71 CTxD/P70 9 A/D converter System control High-speed internal oscillator RESET X1/P121 X2/EXCLK/P122 XT1/P123 XT2/EXCLKS/P124 VDD, VSS, FLMD0 EVDD EVSS 4 Interrupt control On-chip debugger 2 CAN User's Manual U17555EJ3V0UD 25 www..com CHAPTER 1 OUTLINE 1.7 Outline of Functions (1/2) Item Internal memory (bytes) Flash memory (self-programming supported) Bank High-speed RAM Expansion RAM Memory space High-speed system clock (oscillation frequency) Note 1 Note 1 PD78F0881 32 K PD78F0882 48 K PD78F0883 60 K PD78F0884 32 K PD78F0885 48 K PD78F0886 60 K - 1K 1K 2K 2K 64 KB Crystal/ceramic oscillation (X1), external main system clock input (EXCLK) 4 to 20 MHz: VDD = 4.0 to 5.5 V, 4 to 10 MHz: VDD = 2.7 to 5.5 V, 4 to 5 MHz: VDD = 1.8 to 5.5 V 1K 2K 2K Note 1 Internal high-speed oscillation clock (oscillation frequency) Internal low-speed oscillation clock (oscillation frequency) Subsystem clock (oscillation frequency) General-purpose registers Minimum instruction execution time On-chip internal oscillation (8 MHz (TYP.): VDD = 2.7 to 5.5 V) On-chip internal oscillation (240 kHz (TYP.)) Crystal oscillation (XT1), external subsystem clock input (EXCLKS) (32.768 kHz: VDD = 1.8 to 5.5 V) 8 bits x 32 registers (8 bits x 8 registers x 4 banks) 0.1 s/0.2 s/0.4 s/0.8 s/1.6 s (high-speed system clock: @ fXP = 20 MHz operation) 0.25 s/0.5 s/1.0 s/2.0 s/4.0 s (TYP.) (internal oscillator clock: @ fRH = 8 MHz (TYP.) operation) 122 s (subsystem clock: when operating at fXT = 32.768 kHz) Instruction set * 16-bit operation * Multiply/divide (8 bits x 8 bits, 16 bits / 8 bits) * Bit manipulate (set, reset, test, and Boolean operation) * BCD adjust, etc. I/O ports Total: CMOS I/O CMOS output N-ch open-drain I/O 37 33 1 3 Note 2 Total: CMOS I/O CMOS output N-ch open-drain I/O 41 36 1 4 Timers * 16-bit timer/event counter: 2 channels * 8-bit timer/event counter: * 8-bit timer: * Watch timer * Watchdog timer: Timer outputs 8 (PWM output: 4) 2 channels 2 channels 1 channel 1 channel Clock output * 78.125 kHz, 156.25 kHz, 312.5 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz (high-speed system clock: 10 MHz) * 32.768 kHz (subsystem clock: 32.768 kHz) Notes 1. The internal flash memory capacity, internal high-speed RAM capacity, and internal expansion RAM capacity can be changed using the internal memory size switching register (IMS) and the internal expansion RAM size switching register (IXS). 2. Since TM01 does not have the following terminal at 78K0/FC2, the function is restricted in part. PD78F0881, 78F0882, and 78F0883: TI001, TI011, TO01 PD78F0884, 78F0885, and 78F0886: TI001 26 User's Manual U17555EJ3V0UD www..com CHAPTER 1 OUTLINE (2/2) Item Buzzer output PD78F0881 PD78F0882 PD78F0883 PD78F0884 PD78F0885 PD78F0886 1.22 kHz, 2.44 kHz, 4.88 kHz, 9.77 kHz (high-speed system clock: 10 MHz) 10-bit resolution x 8 channels CAN LIN-UART LIN-UART/ CSI Note A/D converter Serial interface 10-bit resolution x 9 channels 1 ch 1 ch 1 ch Multiplier/divider * 16 bit x 16 bit = 32 bit (Multiplication) * 32 bit / 32 bit = 32 bit remainder of 16 bits (Division) Vectored interrupt sources Reset Internal External * Reset using RESET pin * Internal reset by watchdog timer * Internal reset by power-on-clear * Internal reset by low-voltage detector 21 8 On-chip debug function Supply voltage Operating ambient temperature Package VDD = 1.8 to 5.5 V TA = -40 to +85C, -40 to +125C 44-pin plastic LQFP(10x10) Provided 48-pin plastic LQFP (Fine pitch) (7x7) Note Select either of the functions of these alternate-function pins. An outline of the timer is shown below. 16-Bit Timer/ Event Counters 00 to 03 8-Bit Timer/ Event Counters 50 and 51 TM00 TM01 TM02 TM03 Operation mode Function Interval timer External event counter Timer output PPG output PWM output Pulse width measurement Square-wave output Interrupt source 1 ch 1 ch 1 1 - 2 1 2 2 1 1 ch Note 2 8-Bit Timers H0 Watch Timer Watchdog and H1 Timer TM50 1 ch 1 ch 1 - 1 - 1 1 TM51 1 ch 1 ch 1 - 1 - 1 1 TMH0 1 ch - 1 - 1 - 1 1 TMH1 1 ch - 1 - 1 - 1 1 Note 1 - - - - - - - - - - - - - - - - 1 channel - - - - - - 1 1 channel - - - - - - - 1 ch 1 1 Note 2 Note 2 - Note 2 Note2 2 Notes 1. In the watch timer, the watch timer function and interval timer function can be used simultaneously. 2. PD78F0884, 78F0885, and 78F0886 only. Remark TM51 and TMH1 can be used in combination as a carrier generator mode. User's Manual U17555EJ3V0UD 27 www..com CHAPTER 2 PIN FUNCTIONS 2.1 Pin Function List There are three types of pin I/O buffer power supplies: AVREF, EVDD/VDD. The relationship between these power supplies and the pins is shown below. Table 2-1. Pin I/O Buffer Power Supplies Power Supply AVREF P80 to P87, P90 Note Corresponding Pins EVDD/VDD * Port pins other than P80 to P87, P90 * Non-port pins Note Note P90 is PD78F0884, 78F0885, and 78F0886 only. This section explains the names and functions of the pins of the 78K0/FC2. (1) Port pins Table 2-2. Port pins (1/2) Pin Name P00 P01 P06 P10 P11 P12 P13 P14 P15 P16 P17 P30 P31 P32 P33 P40, P41 I/O I/O Port 3. 4-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. Port 4. 2-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. Input INTP3 INTP4/TI51/TO51 - Input Note I/O I/O Port 0. 3-bit I/O port. Function After Reset Input Alternate Function TI000 TI010/TO00 TI011/TO01 Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. I/O Port 1. 8-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. Input SCK10/TxD61 SI10/RxD61 SO10 TxD60 RxD60 TOH0 TOH1/INTP5 TI50/TO50 INTP1 INTP2 Note P06 is PD78F0884, 78F0885, and 78F0886 only. 28 User's Manual U17555EJ3V0UD www..com CHAPTER 2 PIN FUNCTIONS Table 2-2. Port pins (2/2) Pin Name P60 to P63 Note I/O I/O Port 6. 4-bit I/O port Input/output can be specified in 1-bit units. Function N-ch open drain I/O port. After Reset Input Alternate Function - P70 P71 P72 P73 P80 to P87 I/O Port 7. 4-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. Input CTxD CRxD PCL/INTP6 BUZ/INTP7 I/O Port 8. 8-bit I/O port. Input/output can be specified in 1-bit units. Input ANI0 to ANI7 P90 Note I/O Port 9. 1-bit I/O port. Input/output can be specified in 1-bit units. Input ANI8 P120 P121 P122 P123 P124 P130 I/O Port 12. 5-bit I/O port. Only for P120, use of an on-chip pull-up resistor can be specified by a software setting. Input INTP0/EXLVI X1 X2/EXCLK XT1 XT2/EXCLKS Output Port 13. P130 is 1-bit output-only port. P131 is 1-bit I/O port. Output - P131 Note I/O P131 use of an on-chip pull-up resistor can be specified by a software setting. Input Note P63, P90 and P131 are PD78F0884, 78F0885, and 78F0886 only. User's Manual U17555EJ3V0UD 29 www..com CHAPTER 2 PIN FUNCTIONS (2) Non-port pins Table 2-3. Non-port pins (1/2) Pin Name INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTP6 INTP7 SI10 SO10 SCK10 RxD60 RxD61 TxD60 TxD61 TI000 Input External count clock input to 16-bit timer/event counter 00 Capture trigger input to capture registers (CR000, CR010) of 16-bit timer/event counter 00 TI010 Capture trigger input to capture register (CR000) of 16-bit timer/event counter 00 TI011 Capture trigger input to capture register (CR001) of 16-bit timer/event counter 01 TO00 TO01 TI50 TI51 TO50 TO51 TOH0 TOH1 PCL Output Output Input Output 16-bit timer/event counter 00 output 16-bit timer/event counter 01 output External count clock input to 8-bit timer/event counter 50 External count clock input to 8-bit timer/event counter 51 8-bit timer/event counter 50 output 8-bit timer/event counter 51 output 8-bit timer H0 output 8-bit timer H1 output Clock output (for trimming of high-speed system clock, subsystem clock) BUZ ANI0 to ANI8 Note I/O Input Function External interrupt request input for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified After Reset Input Alternate Function P120/EXLVI P30 P31 P32 P33/TI51/TO51 P16/TOH1 P72/PCL P73/BUZ Input Output I/O Input Serial data input to serial interface Serial data output from serial interface Clock input/output for serial interface Serial data input to asynchronous serial interface Input Input Input Input P11/RxD61 P12 P10/TxD61 P14 P11/SI10 Output Serial data output from asynchronous serial interface Input P13 P10/SCK10 Input P00 P01/TO00 P06/TO01 Input P01/TI010 P06/TI011 Input P17/TO50 P33/TO51/INTP4 Input P17/TI50 P33/TI51/INTP4 P15 P16/INTP5 Input P72/INTP6 Output Input Buzzer output A/D converter analog input Input Input P73/INTP7 P80 to P87, P90 30 User's Manual U17555EJ3V0UD www..com CHAPTER 2 PIN FUNCTIONS Table 2-3. Non-port pins (2/2) Pin Name CTxD CRxD AVREF I/O Input Output Input - Input Input - Input - Input Input Input - - - - - - External clock input for main system clock External clock input for subsystem clock Potential input for external low-voltage detection Positive power supply (except for ports) Positive power supply for ports Ground potential (except for ports) Ground potential for ports Flash memory programming mode setting. This is the pin for connecting regulator output (2.5 V) stabilization capacitance for internal operation. Connect this pin to VSS via a capacitor (0.47 to 1 F: recommended). Connecting resonator for subsystem clock CAN transmit data output CAN receive data input A/D converter reference voltage input and positive power supply for port 2 AVSS A/D converter ground potential. Make the same potential as EVSS or VSS. RESET X1 X2 XT1 XT2 EXCLK EXCLKS EXLVI VDD EVDD VSS EVSS FLMD0 REGC System reset input Connecting resonator for high-speed system clock Input Input Input Input Input Input Input - - - - - - - P121 P122/EXCLK P123 P124/EXCLKS P122/X2 P124/XT2 P120/INTP0 - - - - - - - - - Function After Reset Input Input - Alternate Function P70 P71 - User's Manual U17555EJ3V0UD 31 www..com CHAPTER 2 PIN FUNCTIONS 2.2 Description of Pin Functions 2.2.1 P00, P01, P06 (port 0) P00, P01 and P06 function as a 3-bit I/O port. These pins also function as timer I/O. The following operation modes can be specified in 1-bit units. (1) Port mode P00, P01 and P06 function as 3-bit I/O port. P00, P01 and P06 can be set to input or output in 1-bit units using port mode register 0 (PM0). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 0 (PU0). (2) Control mode P00, P01 and P06 function as timer I/O. (a) TI000 These is the pin for inputting an external count clock to 16-bit timer/event counters 00 and are also for inputting a capture trigger signal to the capture registers (CR000) of 16-bit timer/event counters 00. (b) TI010, TI011 These are the pin for inputting a capture trigger signal to the capture register (CR010, CR011) of 16-bit timer/event counters 00 and 01. (c) TO00, TO01 These are timer output pin. Caution P06 is PD78F0884, 78F0885, and 78F0886 only. 32 User's Manual U17555EJ3V0UD www..com CHAPTER 2 PIN FUNCTIONS 2.2.2 P10 to P17 (port 1) P10 to P17 function as an 8-bit I/O port. These pins also function as pins for external interrupt request input, serial interface data I/O, clock I/O, and timer I/O. The following operation modes can be specified in 1-bit units. (1) Port mode P10 to P17 function as an 8-bit I/O port. P10 to P17 can be set to input or output in 1-bit units using port mode register 1 (PM1). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 1 (PU1). (2) Control mode P10 to P17 function as external interrupt request input, serial interface data I/O, clock I/O, and timer I/O. (a) SI10 This is a serial interface serial data input pin. (b) SO10 This is a serial interface serial data output pin. (c) SCK10 This is a serial interface serial clock I/O pin. (d) RxD60, RxD61 These are the serial data input pins of the asynchronous serial interface. (e) TxD60, TxD61 These are the serial data output pins of the asynchronous serial interface. (f) TI50 This is the pin for inputting an external count clock to 8-bit timer/event counter 50. (g) TO50, TOH0, and TOH1 These are timer output pins. (h) INTP5 This is an external interrupt request input pin for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. User's Manual U17555EJ3V0UD 33 www..com CHAPTER 2 PIN FUNCTIONS 2.2.3 P30 to P33 (port 3) P30 to P33 function as a 4-bit I/O port. These pins also function as pins for external interrupt request input and timer I/O. The following operation modes can be specified in 1-bit units. (1) Port mode P30 to P33 function as a 4-bit I/O port. P30 to P33 can be set to input or output in 1-bit units using port mode register 3 (PM3). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 3 (PU3). (2) Control mode P30 to P33 function as external interrupt request input pins and timer I/O pins. (a) INTP1 to INTP4 These are the external interrupt request input pins for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. (b) TI51 This is an external count clock input pin to 8-bit timer/event counter 51. (c) TO51 This is a timer output pin. Cautions 1. Be sure to pull the P31/INTP2 pin down before a reset release, to prevent malfunction. 2. Connect P31/INTP2 as follows when writing the flash memory with a flash programmer. - P31/INTP2: Connect to EVSS via a resistor (10 k: recommended). The above connection is not necessary when writing the flash memory by means of self programming. Remark P31/INTP2 and P32/INTP3 can be used as on-chip debug mode setting pins when the on-chip debug function is used. For details, refer to CHAPTER 24 ON-CHIP DEBUG FUNCTION. 2.2.4 P40, P41 (port 4) P40, P41 function as a 2-bit I/O port. P40, P41 can be set to input or output in 1-bit units using port mode register 4 (PM4). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 4 (PU4). 2.2.5 P60 to P63 (port 6) P60 to P63 function as a 4-bit I/O port. P60 to P63 can be set to input port or output port in 1-bit units using port mode register 6 (PM6) P60 to P63 are N-ch open-drain pins. Caution P63 is PD78F0884, 78F0885, and 78F0886 only. 34 User's Manual U17555EJ3V0UD www..com CHAPTER 2 PIN FUNCTIONS 2.2.6 P70 to P73 (port 7) P70 to P73 function as a 4-bit I/O port. These pins also function as external interrupt request input, clock output pins, buzzer output pins, CAN I/F I/O. The following operation modes can be specified in 1-bit units. (1) Port mode P70 to P73 function as a 4-bit I/O port. P70 to P73 can be set to input or output in 1-bit units using port mode register 7 (PM7). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 7 (PU7). (2) Control mode P70 to P73 function as external interrupt request input, output pins, buzzer output pins, CAN I/F I/O. (a) INTP6, INTP7 These are the external interrupt request input pins for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. (b) CRxD This is the CAN serial receive data input pin. (c) CTxD This is the CAN serial transmit data output pin. (d) PCL This is a clock output pin. (e) BUZ This is a buzzer output pin. 2.2.7 P80 to P87 (port 8) P80 to P87 function as an 8-bit I/O port. These pins also function as pins for A/D converter analog input. The following operation modes can be specified in 1-bit units. (1) Port mode P80 to P87 function as an 8-bit I/O port. P80 to P87 can be set to input or output in 1-bit units using port mode register 8 (PM8). (2) Control mode P80 to P87 function as A/D converter analog input pins (ANI0 to ANI7). When using these pins as analog input pins, see (5) P80/ANI0 to P87/ANI7, P90/ANI8 in 12.6 Cautions for A/D Converter. Caution P80/ANI0 to P87/ANI7 is set in the analog input mode after release of reset. User's Manual U17555EJ3V0UD 35 www..com CHAPTER 2 PIN FUNCTIONS 2.2.9 P120 to P124 (port 12) P120 to P124 function as a 5-bit I/O port. These pins also function as pins for external interrupt request input, external clock input for main system clock, external clock input for subsystem clock and potential input for external low-voltage detection. The following operation modes can be specified in 1-bit units. (1) Port mode P120 to P124 function as a 5-bit I/O port. P120 to P124 can be set to input or output using port mode register 12 (PM12). Only for P120, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 12 (PU12). (2) Control mode P120 to P124 function as pins for external interrupt request input, potential input for external low-voltage detection, resonator connection for main system clock, resonator connection for subsystem clock, external clock input for main system clock and external clock input for subsystem clock. (a) INTP0 This functions as an external interrupt request input for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. (b) EXLVI This is a potential input pin for external low-voltage detection. (c) X1, X2 These are the pins for connecting a resonator for high-speed system clock. When supplying an external clock, input a signal to the X1 pin and input the inverse signal to the X2 pin. Caution Connect P121/X1 as follows when writing the flash memory with a flash programmer. - P121/X1: When using this pin as a port, connect it to VSS via a resistor (10 k: recommended) (in the input mode) or leave it open (in the output mode). The above connection is not necessary when writing the flash memory by means of self programming. Remark The X1 and X2 pins can be used as on-chip debug mode setting pins when the on-chip debug function is used. For details, refer to CHAPTER 24 ON-CHIP DEBUG FUNCTION. 36 User's Manual U17555EJ3V0UD www..com CHAPTER 2 PIN FUNCTIONS (d) EXCLK This is an external clock input pin for main system clock. (e) XT1, XT2 These are the pins for connecting a resonator for subsystem clock. When supplying an external clock, input a signal to the XT1 pin and input the inverse signal to the XT2 pin. (f) EXCLKS This is an external clock input pin for subsystem clock. 2.2.10 P130, P131 (port 13) P130 functions as a 1-bit output-only port. P131 function as a 1-bit I/O port. P131 can be set to input or output in 1-bit units using port mode register 13 (PM13). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 13 (PU13). Caution P131 is PD78F0884, 78F0885, and 78F0886 only. 2.2.11 AVREF This is the A/D converter reference voltage input pin. Note When the A/D converter is not used, connect this pin directly to EVDD or VDD . Note Connect port 8 and port 9 directly to EVDD when it is used as a digital port. 2.2.12 AVSS This is the A/D converter ground potential pin. Even when the A/D converter is not used, always use this pin with the same potential as the EVSS pin or VSS pin. 2.2.13 RESET This is the active-low system reset input pin. REGC VSS Caution Keep the wiring length as short as possible for the broken-line part in the above figure. 2.2.15 VDD and EVDD VDD is the positive power supply pin for other than ports. EVDD is the positive power supply pin for ports. 2.2.16 VSS and EVSS VSS is the ground potential pin for other than ports. EVSS is the ground potential pin for ports. User's Manual U17555EJ3V0UD 37 www..com CHAPTER 2 PIN FUNCTIONS 2.2.17 FLMD0 This is a pin for setting flash memory programming mode. Connect to EVSS or VSS in the normal operation mode. In flash memory programming mode, be sure to connect this pin to the flash programmer. 38 User's Manual U17555EJ3V0UD www..com CHAPTER 2 PIN FUNCTIONS 2.3 Pin I/O Circuits and Recommended Connection of Unused Pins Table 2-4 shows the types of pin I/O circuits and the recommended connections of unused pins. Refer to Figure 2-1 for the configuration of the I/O circuit of each type. Table 2-4. Pin I/O Circuit Types (1/2) Pin Name P00/TI000 P01/TI010/TO00 P06/TI011/TO01 Note 1 I/O Circuit Type 5-AH I/O I/O Recommended Connection of Unused Pins Input: Independently connect to EVDD or EVSS via a resistor. Output: Leave open. P10/SCK10/TxD61 P11/SI10/RxD61 P12/SO10 P13/TxD60 P14/RxD60 P15/TOH0 P16/TOH1/INTP5 P17/TI50/TO50 P30/INTP1 P31/INTP2 P32/INTP3 P33/TI51/TO51/INTP4 P40, P41 P60 to P63 Note 1 Note 2 5-H 5-AH 5-H 5-AH 5-H 13-P Input: Connect to EVSS. Output: Leave this pin open at low-level output after clearing the output latch of the port to 0. Input: Independently connect to EVDD or EVSS via a resistor. Output: Leave open. P70/CTxD P71/CRxD P72/PCL/INTP6 P73/BUZ/INTP7 P80/ANI0 to P87/ANI7 Note 3 5-H 5-AH 11-G I/O P90/ANI8 Note 1 Input: Independently connect to EVDD or EVSS via a resistor. Output: Leave open. Notes 1. 2. P06, P63 and P90 are PD78F0884, 78F0885, and 78F0886 only. Connect P31/INTP2 as follows when writing the flash memory with a flash programmer. - P31/INTP2: Connect to EVSS via a resistor (10 k: recommended). The above connection is not necessary when writing the flash memory by means of self programming. 3. P80/ANI0 to P87/ANI7 and P90/ANI8 is set in the analog input mode after release of reset. User's Manual U17555EJ3V0UD 39 www..com CHAPTER 2 PIN FUNCTIONS Table 2-4. Pin I/O Circuit Types (2/2) Pin Name P120/INTP0/EXLVI I/O Circuit Type 5-AH I/O I/O Recommended Connection of Unused Pins Input: Independently connect to EVDD or EVSS via a resistor. Output: Leave open. P121/X1 Note 1, 2 37 Note 1 I/O Input: Independently connect to EVDD or P122/X2/EXCLK P123/XT1 Note 1 EVSS via a resistor. Output: Leave open. P124/XT2/EXCLKS P130 P131 Note 3 Note 1 3-C 5-AH Output I/O Leave open. Input: Independently connect to EVDD or EVSS via a resistor. Output: Leave open. RESET AVREF AVSS FLMD0 2 - Input - Connect to EVDD or VDD. Connect directly to EVDD or VDD Note 4 . Connect directly to EVSS or VSS. Connect to EVSS or VSS. Notes 1. Use the recommended connection above in I/O port mode (see Figure 5-6 Format of Clock Operation Mode Select Register (OSCCTL)) when these pins are not used. 2. Connect P121/X1 as follows when writing the flash memory with a flash programmer. - P121/X1: When using this pin as a port, connect it to VSS via a resistor (10 k: recommended) (in the input mode) or leave it open (in the output mode). The above connection is not necessary when writing the flash memory by means of self programming. 3. 4. P131 is PD78F0884, 78F0885, and 78F0886 only. Connect port 8 directly to EVDD when it is used as a digital port. 40 User's Manual U17555EJ3V0UD www..com CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin I/O Circuit List (1/2) Type 2 Type 5-H EVDD Pullup enable P-ch EVDD IN Output data Schmitt-triggered input with hysteresis characteristics Output disable P-ch IN/OUT N-ch EVss Input enable Type 3-C Type 11-G AVREF EVDD P-ch Data N-ch Vss OUT Comparator + _ AVREF (threshold voltage) AVSS Input enable Data P-ch IN/OUT Output disable N-ch P-ch AVSS N-ch Type 5-AH EVDD Type 13-P Pull-up enable P-ch IN/OUT Data Output disable EVss N-ch EVDD Data P-ch IN/OUT Output disable N-ch input enable EVSS Input enable User's Manual U17555EJ3V0UD 41 www..com CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin I/O Circuit List (2/2) Type 37 Reset Data Output disable Input enable Reset Data Output disable Input enable EVDD P-ch X2, XT2 N-ch EVSS P-ch N-ch EVDD P-ch N-ch EVSS X1, XT1 42 User's Manual U17555EJ3V0UD www..com CHAPTER 3 CPU ARCHITECTURE 3.1 Memory Space Products in the 78K0/FC2 can each access a 64 KB memory space. Figures 3-1 to 3-3 show the memory map. Caution Regardless of the internal memory capacity, the initial values of the internal memory size switching register (IMS) and internal expansion RAM size switching register (IXS) of the 78K0/FC2 is fixed (IMS = CFH, IXS = 0CH). Therefore, set the value corresponding to each product as indicated below. Table 3-1. Set Values of Internal Memory Size Switching Register (IMS) and Internal Expansion RAM Size Switching Register (IXS) Flash Memory Version IMS C8H CCH CFH 0AH 08H 08H IXS PD78F0881, 78F0884 PD78F0882, 78F0885 PD78F0883, 78F0886 User's Manual U17555EJ3V0UD 43 www..com CHAPTER 3 CPU ARCHITECTURE Figure 3-1. Memory Map (PD78F0881, 78F0884) FFFFH Special function registers (SFR) 256 x 8 bits General-purpose registers 32 x 8 bits Internal high-speed RAM 1024 x 8 bits Note 1 FB00H FAFFH FA00H F9FFH Data memory space F800H F7FFH Internal expansion RAM 1024 x 8 bits 0800H 07FFH Program area 1915 x 8 bits Reserved 8000H Program 7FFFH memory space 0190H 018FH 0083H 0082H 0000H 0085H 0084H 0080H 007FH Option byte areaNote 3 5 x 8 bits CALLT table area 64 x 8 bits Boot cluster 0Note 4 FF20H FF1FH Short direct addressing 7FFFH FE20H FE1FH FE10H FE0FH Program area 1FFFH 1085H 1084H 1080H 107FH Option byte areaNote 3 5 x 8 bits FF00H FEFFH FEE0H FEDFH AFCAN area (256 x 8 bits) Reserved Boot cluster 1 Program area 1000H 0FFFH CALLF entry area 2048 x 8 bits RAM space in which instruction can be fetched F400H F3FFH Flash memory 32768 x 8 bits Note 2 0040H 003FH Vector table area 64 x 8 bits 0000H Notes 1. During on-chip debugging, use of this area is disabled since it is used as the user data backup area for communication. 2. During on-chip debugging, use of this area is disabled since it is used as the communication command area (269 bytes). 7FFFH EC00H EBFFH Block 1FH Set the option bytes to 0080H to 0084H and 1080H to 1084H. Security 4. Writing boot cluster 0 can be prohibited depending on the setting of security (see 23.8 07FFH 0400H 03FFH 0000H Block 01H Block 00H 1 KB 44 User's Manual U17555EJ3V0UD www..com CHAPTER 3 CPU ARCHITECTURE Figure 3-2. Memory Map (PD78F0882, 78F0884) FFFFH Special function registers (SFR) 256 x 8 bits General-purpose registers 32 x 8 bits Internal high-speed RAM 1024 x 8 bits Note 1 FB00H FAFFH FA00H F9FFH Data memory space F800H F7FFH Internal expansion RAM 2048 x 8 bits FF20H FF1FH Short direct addressing BFFFH FE20H FE1FH FE10H FE0FH Program area 1FFFH 1085H 1084H 1080H 107FH Option byte areaNote 3 5 x 8 bits FF00H FEFFH FEE0H FEDFH AFCAN area (256 x 8 bits) Reserved Boot cluster 1 Program area 1000H 0FFFH CALLF entry area 2048 x 8 bits 0800H 07FFH Program area 1915 x 8 bits Reserved 0085H 0084H 0080H 007FH Option byte areaNote 3 5 x 8 bits CALLT table area 64 x 8 bits Boot cluster 0Note 4 RAM space in which instruction can be fetched F000H EFFFH C000H BFFFH Program memory space 0190H 018FH 0083H 0082H 0000H Flash memory 49152 x 8 bits Note 2 0040H 003FH Vector table area 64 x 8 bits 0000H Notes 1. During on-chip debugging, use of this area is disabled since it is used as the user data backup area for communication. 2. During on-chip debugging, use of this area is disabled since it is used as the communication command area (269 byte). BFFFH EC00H EBFFH Block 2FH Set the option bytes to 0080H to 0084H and 1080H to 1084H. Security 4. Writing boot cluster 0 can be prohibited depending on the setting of security (see 23.8 07FFH 0400H 03FFH 0000H Block 01H Block 00H 1 KB User's Manual U17555EJ3V0UD 45 www..com CHAPTER 3 CPU ARCHITECTURE Figure 3-3. Memory Map (PD78F0883, 78F0886) FFFFH Special function registers (SFR) 256 x 8 bits General-purpose registers 32 x 8 bits Internal high-speed RAM 1024 x 8 bits Note 1 FB00H FAFFH FA00H F9FFH Data memory space F800H F7FFH Internal expansion RAM 2048 x 8 bits FF20H FF1FH Short direct addressing EFFFH FE20H FE1FH FE10H FE0FH Program area 1FFFH 1085H 1084H 1080H 107FH Option byte areaNote 3 5 x 8 bits FF00H FEFFH FEE0H FEDFH AFCAN area (256 x 8 bits) Reserved Boot cluster 1 Program area 1000H 0FFFH CALLF entry area 2048 x 8 bits 0800H 07FFH Program area 1915 x 8 bits 0085H 0084H 0080H 007FH Flash memory 61440 x 8 bits 0040H 003FH Note 2 Option byte areaNote 3 5 x 8 bits CALLT table area 64 x 8 bits Boot cluster 0Note 4 RAM space in which instruction can be fetched F000H EFFFH Program memory space 0190H 018FH 0083H 0082H 0000H Vector table area 64 x 8 bits 0000H Notes 1. During on-chip debugging, use of this area is disabled since it is used as the user data backup area for communication. 2. During on-chip debugging, use of this area is disabled since it is used as the communication command area (269 bytes). EFFFH EC00H EBFFH Block 3BH Set the option bytes to 0080H to 0084H and 1080H to 1084H. Security 4. Writing boot cluster 0 can be prohibited depending on the setting of security (see 23.8 07FFH 0400H 03FFH 0000H Block 01H Block 00H 1 KB 46 User's Manual U17555EJ3V0UD www..com CHAPTER 3 CPU ARCHITECTURE Correspondence between the address values and block numbers in the flash memory are shown below. Address Value Block Number 0000H to 03FFH 0400H to 07FFH 0800H to 0BFFH 0C00H to 0FFFH 1000H to 13FFH 1400H to 17FFH 1800H to 1BFFH 1C00H to 1FFFH 2000H to 23FFH 2400H to 27FFH 2800H to 2BFFH 2C00H to 2FFFH 3000H to 33FFH 3400H to 37FFH 3800H to 3BFFH 3C00H to 3FFFH 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 4000H to 43FFH 4400H to 47FFH 4800H to 4BFFH 4C00H to 4FFFH 5000H to 53FFH 5400H to 57FFH 5800H to 5BFFH 5C00H to 5FFFH 6000H to 63FFH 6400H to 67FFH 6800H to 6BFFH 6C00H to 6FFFH 7000H to 73FFH 7400H to 77FFH 7800H to 7BFFH 7C00H to 7FFFH Address Value Block Number 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 8000H to 83FFH 8400H to 87FFH 8800H to 8BFFH 8C00H to 8FFFH 9000H to 93FFH 9400H to 97FFH 9800H to 9BFFH 9C00H to 9FFFH A000H to A3FFH A400H to A7FFH A800H to ABFFH AC00H to AFFFH B000H to B3FFH B400H to B7FFH B800H to BBFFH BC00H to BFFFH Address Value Block Number 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH C000H to C3FFH C400H to C7FFH C800H to CBFFH CC00H to CFFFH D000H to D3FFH D400H to D7FFH D800H to DBFFH DC00H to DFFFH E000H to E3FFH E400H to E7FFH E800H to EBFFH EC00H to EFFFH Address Value Block Number 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH Remark PD78F0881, 78F0884: Block numbers 00H to 1FH PD78F0882, 78F0885: Block numbers 00H to 2FH PD78F0883, 78F0886: Block numbers 00H to 3BH User's Manual U17555EJ3V0UD 47 www..com CHAPTER 3 CPU ARCHITECTURE 3.1.1 Internal program memory space The internal program memory space stores the program and table data. Normally, it is addressed with the program counter (PC). 78K0/FC2 products incorporate internal ROM (flash memory), as shown below. Table 3-3. Internal ROM Capacity Part Number Structure Internal ROM Capacity 32768 x 8 bits (0000H to 7FFFH) 49152 x 8 bits (0000H to BFFFH) 61440 x 8 bits (0000H to EFFFH) PD78F0881, 78F0884 PD78F0882, 78F0885 PD78F0893, 78F0886 Flash memory The internal program memory space is divided into the following areas. (1) Vector code area The 64-byte area 0000H to 003FH is reserved as a Vector code area. The program start addresses for branch upon reset signal input or generation of each interrupt request are stored in the Vector code area. Of the 16-bit address, the lower 8 bits are stored at even addresses and the higher 8 bits are stored at odd addresses. Table 3-4. Vector Code Vector Code Address 0000H Interrupt Source RESET input, POC, LVI, WDT 0004H 0006H 0008H 000AH 000CH 000EH 0010H 0012H 0014H 0016H 0018H 001AH 001CH 001EH INTLVI INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTC0ERR INTC0WUP INTC0REC INTC0TRX INTSRE60 INTSR60 INTST60 Vector Code Address 0020H 0022H 0024H 0026H 0028H 002AH 002CH 002EH 0030H 0032H 0034H 0036H 003AH 003CH 003EH Interrupt Source INTCSI10/INTSRE61 INTP6/INTSR61 INTP7/INTST61 INTTMH1 INTTMH0 INTTM50 INTTM000 INTTM010 INTAD INTWTI/INTDMU INTTM51 INTWT INTTM001 INTTM011 BRK (2) CALLT instruction table area The 64-byte area 0040H to 007FH can store the subroutine entry address of a 1-byte call instruction (CALLT). (3) Option byte area The option byte area is assigned to the 1-byte area of 0080H. Refer to CHAPTER 22 OPTION BYTE for details. 48 User's Manual U17555EJ3V0UD www..com CHAPTER 3 CPU ARCHITECTURE (4) CALLF instruction entry area The area 0800H to 0FFFH can perform a direct subroutine call with a 2-byte call instruction (CALLF). Part Number Internal High-Speed RAM 1024 x 8 bits (FB00H to FEFFH) PD78F0881, 78F0884 PD78F0882, 78F0885 PD78F0883, 78F0886 The 32-byte area FEE0H to FEFFH is assigned to four general-purpose register banks consisting of eight 8-bit registers per one bank. This area cannot be used as a program area in which instructions are written and executed. The internal high-speed RAM can also be used as a stack memory. (2) Internal expansion RAM Table 3-6. Internal Expansion RAM Capacity Part Number Internal Expansion RAM 1024 x 8 bits (F400H to F7FFH) 2048 x 8 bits (F000H to F7FFH) PD78F0881, 78F0884 PD78F0882, 78F0885 PD78F0883, 78F0886 The internal expansion RAM can also be used as a normal data area similar to the internal high-speed RAM, as well as a program area in which instructions can be written and executed. The internal expansion RAM cannot be used as a stack memory. 3.1.3 Special function register (SFR) area On-chip peripheral hardware special function registers (SFRs) are allocated in the area FF00H to FFFFH (refer to Table 3-7 Special Function Register List in 3.2.3 Special Function Registers (SFRs)). Caution Do not access addresses to which SFRs are not assigned. User's Manual U17555EJ3V0UD 49 www..com CHAPTER 3 CPU ARCHITECTURE 3.1.4 Data memory addressing Addressing refers to the method of specifying the address of the instruction to be executed next or the address of the register or memory relevant to the execution of instructions. Several addressing modes are provided for addressing the memory relevant to the execution of instructions for the 78K0/FC2, based on operability and other considerations. For areas containing data memory in particular, special addressing methods designed for the functions of special function registers (SFR) and general-purpose registers are available for use. Figure 3-4 to 3-6 show correspondence between data memory and addressing. For details of each addressing mode, refer to 3.4 Operand Address Addressing. 50 User's Manual U17555EJ3V0UD www..com CHAPTER 3 CPU ARCHITECTURE Figure 3-4. Correspondence Between Data Memory and Addressing (PD78F0881, PD78F0884) FFFFH Special function registers (SFR) 256 x 8 bits SFR addressing FF20H FF1FH FF00H FEFFH FEE0H FEDFH General-purpose registers 32 x 8 bits Register addressing Short direct addressing Internal high-speed RAM 1024 x 8 bits Note 1 FB00H FAFFH FA00H F9FFH AFCAN area (256 x 8 bits) FE20H FE1FH FE10H FE0FH Reserved F800H F7FFH Direct addressing Register indirect addressing Based addressing Based indexed addressing Internal expansion RAM 1024 x 8 bits F400H F3FFH Reserved 8000H 7FFFH 0190H 018FH 0083H 0082H 0000H Flash memory 32768 x 8 bits Note 2 Notes 1. During on-chip debugging, use of this area is disabled since it is used as the user data backup area for communication. 2. During on-chip debugging, use of this area is disabled since it is used as the communication command area (269 bytes). User's Manual U17555EJ3V0UD 51 www..com CHAPTER 3 CPU ARCHITECTURE Figure 3-5. Correspondence Between Data Memory and Addressing (PD78F0882, 78F0885) FFFFH Special function registers (SFR) 256 x 8 bits SFR addressing FF20H FF1FH FF00H FEFFH FEE0H FEDFH General-purpose registers 32 x 8 bits Internal high-speed RAM 1024 x 8 bits Note 1 Register addressing Short direct addressing FE20H FE1FH FE10H FE0FH FB00H FAFFH FA00H F9FFH AFCAN area (256 x 8 bits) Direct addressing Register indirect addressing Based addressing Based indexed addressing Internal expansion RAM 2048 x 8 bits Reserved F800H F7FFH F000H EFFFH Reserved C000H BFFFH Flash memory 49152 x 8 bits 0190H 018FH Note 2 0083H 0082H 0000H Notes 1. During on-chip debugging, use of this area is disabled since it is used as the user data backup area for communication. 2. During on-chip debugging, use of this area is disabled since it is used as the communication command area (269 bytes). 52 User's Manual U17555EJ3V0UD www..com CHAPTER 3 CPU ARCHITECTURE Figure 3-6. Correspondence Between Data Memory and Addressing (PD78F0883, 78F0886) FFFFH Special function registers (SFR) 256 x 8 bits SFR addressing FF20H FF1FH FF00H FEFFH FEE0H FEDFH General-purpose registers 32 x 8 bits Internal high-speed RAM 1024 x 8 bits Note 1 Register addressing Short direct addressing FE20H FE1FH FE10H FE0FH FB00H FAFFH FA00H F9FFH AFCAN area (256 x 8 bits) Direct addressing Register indirect addressing Based addressing Based indexed addressing Internal expansion RAM 2048 x 8 bits Reserved F800H F7FFH F000H EFFFH Flash memory 61440 x 8 bits 0190H 018FH Note 2 0083H 0082H 0000H Notes 1. During on-chip debugging, use of this area is disabled since it is used as the user data backup area for communication. 2. During on-chip debugging, use of this area is disabled since it is used as the communication command area (269 bytes). User's Manual U17555EJ3V0UD 53 www..com CHAPTER 3 CPU ARCHITECTURE 3.2 Processor Registers 78K0/FC2 products incorporate the following processor registers. 3.2.1 Control registers The control registers control the program sequence, statuses and stack memory. The control registers consist of a program counter (PC), a program status word (PSW) and a stack pointer (SP). (1) Program counter (PC) The program counter is a 16-bit register that holds the address information of the next program to be executed. In normal operation, the PC is automatically incremented according to the number of bytes of the instruction to be fetched. When a branch instruction is executed, immediate data and register contents are set. Reset signal generation sets the reset Vector code values at addresses 0000H and 0001H to the program counter. Figure 3-7. Format of Program Counter 15 PC PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 0 PC0 (2) Program status word (PSW) The program status word is an 8-bit register consisting of various flags set/reset by instruction execution. Program status word contents are automatically stacked upon interrupt request generation or PUSH PSW instruction execution and are restored upon execution of the RETB, RETI and POP PSW instructions. Reset signal generation sets the PSW to 02H. Figure 3-8. Format of Program Status Word 7 PSW IE Z RBS1 AC RBS0 0 ISP 0 CY (a) Interrupt enable flag (IE) This flag controls the interrupt request acknowledge operations of the CPU. When 0, the IE flag is set to the interrupt disabled (DI) state, and all maskable interrupt requests are disabled. Other interrupt requests are all disabled. When 1, the IE flag is set to the interrupt enabled (EI) state and interrupt request acknowledgement is controlled with an in-service priority flag (ISP), an interrupt mask flag for various interrupt sources, and a priority specification flag. The IE flag is reset (0) upon DI instruction execution or interrupt acknowledgement and is set (1) upon EI instruction execution. (b) Zero flag (Z) When the operation result is zero, this flag is set (1). It is reset (0) in all other cases. (c) Register bank select flags (RBS0 and RBS1) These are 2-bit flags to select one of the four register banks. In these flags, the 2-bit information that indicates the register bank selected by SEL RBn instruction execution is stored. 54 User's Manual U17555EJ3V0UD www..com CHAPTER 3 CPU ARCHITECTURE (d) Auxiliary carry flag (AC) If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). It is reset (0) in all other cases. (e) In-service priority flag (ISP) This flag manages the priority of acknowledgeable maskable vectored interrupts. When this flag is 0, lowlevel vectored interrupt requests specified by a priority specification flag register (PR0L, PR0H, PR1L, PR1H) (refer to 16.3 (3) Priority specification flag registers (PR0L, PR0H, PR1L, PR1H)) can not be acknowledged. Actual request acknowledgement is controlled by the interrupt enable flag (IE). (f) Carry flag (CY) This flag stores overflow and underflow upon add/subtract instruction execution. It stores the shift-out value upon rotate instruction execution and functions as a bit accumulator during bit operation instruction execution. (3) Stack pointer (SP) This is a 16-bit register to hold the start address of the memory stack area. Only the internal high-speed RAM area can be set as the stack area. Figure 3-9 Format of Stack Pointer 15 SP SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 0 SP0 The SP is decremented ahead of write (save) to the stack memory and is incremented after read (restored) from the stack memory. Each stack operation saves/restores data as shown in Figures 3-10 and 3-11. Caution Since reset signal generation makes the SP contents undefined, be sure to initialize the SP before using the stack. User's Manual U17555EJ3V0UD 55 www..com CHAPTER 3 CPU ARCHITECTURE Figure 3-10. Data to Be Saved to Stack Memory (a) PUSH rp instruction (when SP = FEE0H) SP FEE0H FEE0H FEDFH Register pair higher Register pair lower SP FEDEH FEDEH (b) CALL, CALLF, CALLT instructions (when SP = FEE0H) SP FEE0H FEE0H FEDFH PC15 to PC8 PC7 to PC0 SP FEDEH FEDEH (c) Interrupt, BRK instructions (when SP = FEE0H) SP FEE0H FEE0H FEDFH FEDEH PSW PC15 to PC8 PC7 to PC0 SP FEDDH FEDDH 56 User's Manual U17555EJ3V0UD www..com CHAPTER 3 CPU ARCHITECTURE Figure 3-11. Data to Be Restored from Stack Memory (a) POP rp instruction (when SP = FEDEH) SP FEE0H FEE0H FEDFH Register pair higher Register pair lower SP FEDEH FEDEH (b) RET instruction (when SP = FEDEH) SP FEE0H FEE0H FEDFH PC15 to PC8 PC7 to PC0 SP FEDEH FEDEH (c) RETI, RETB instructions (when SP = FEDDH) SP FEE0H FEE0H FEDFH FEDEH PSW PC15 to PC8 PC7 to PC0 SP FEDDH FEDDH User's Manual U17555EJ3V0UD 57 www..com CHAPTER 3 CPU ARCHITECTURE 3.2.2 General-purpose registers General-purpose registers are mapped at particular addresses (FEE0H to FEFFH) of the data memory. The general-purpose registers consists of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L, and H). Each register can be used as an 8-bit register, and two 8-bit registers can also be used in a pair as a 16-bit register (AX, BC, DE, and HL). These registers can be described in terms of function names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL) and absolute names (R0 to R7 and RP0 to RP3). Register banks to be used for instruction execution are set by the CPU control instruction (SEL RBn). Because of the 4-register bank configuration, an efficient program can be created by switching between a register for normal processing and a register for interrupts for each bank. Figure 3-12. Configuration of General-Purpose Registers (a) Absolute name 16-bit processing FEFFH R7 BANK0 FEF8H RP3 R6 R5 BANK1 FEF0H RP1 R2 R1 BANK3 FEE0H 15 0 7 0 RP0 R0 RP2 R4 R3 BANK2 FEE8H 8-bit processing (b) Function name 16-bit processing FEFFH H BANK0 FEF8H HL L D BANK1 FEF0H BC C A BANK3 FEE0H 15 0 7 0 AX X DE E B BANK2 FEE8H 8-bit processing 58 User's Manual U17555EJ3V0UD www..com CHAPTER 3 CPU ARCHITECTURE 3.2.3 Special Function Registers (SFRs) Unlike a general-purpose register, each special function register has a special function. SFRs are allocated to the FF00H to FFFFH area. Special function registers can be manipulated like general-purpose registers, using operation, transfer and bit manipulation instructions. The manipulatable bit units, 1, 8, and 16, depend on the special function register type. Each manipulation bit unit can be specified as follows. * 1-bit manipulation Describe the symbol reserved by the assembler for the 1-bit manipulation instruction operand (sfr.bit). This manipulation can also be specified with an address. * 8-bit manipulation Describe the symbol reserved by the assembler for the 8-bit manipulation instruction operand (sfr). This manipulation can also be specified with an address. * 16-bit manipulation Describe the symbol reserved by the assembler for the 16-bit manipulation instruction operand (sfrp). When specifying an address, describe an even address. Table 3-7 gives a list of the special function registers. The meanings of items in the table are as follows. * Symbol Symbol indicating the address of a special function register. It is a reserved word in the RA78K0, and is defined by the header file "sfrbit.h" in the CC78K0. When using the RA78K0, ID78K0-NS, ID78K0, or SM78K0, symbols can be written as an instruction operand. * R/W Indicates whether the corresponding special function register can be read or written. R/W: Read/write enable R: W: Read only Write only * Manipulatable bit units Indicates the manipulatable bit unit (1, 8, or 16). "-" indicates a bit unit for which manipulation is not possible. * After reset Indicates each register status upon reset signal generation. User's Manual U17555EJ3V0UD 59 www..com CHAPTER 3 CPU ARCHITECTURE Table 3-7. Special Function Register List (1/5) Address Special Function Register (SFR) Name Symbol R/W Manipulatable Bit Unit 1 Bit FF00H FF01H FF02H FF03H FF04H FF06H FF07H FF08H FF09H FF0AH FF0BH FF0CH FF0DH FF0EH FF0FH FF10H FF11H FF12H FF13H FF14H FF15H FF16H FF17H FF18H FF19H FF1AH FF1BH FF1FH FF20H FF21H FF22H FF23H FF24H FF26H FF27H FF28H FF29H FF2AH FF2BH 8-bit timer counter 50 8-bit timer compare register 50 10- bit A/D conversion result register 8-bit A/D conversion result register 8-bit timer H compare register 01 8-bit timer H compare register 11 8-bit timer counter 51 Port mode register 0 Port mode register 1 A/D port configuration register Port mode register 3 Port mode register 4 Port mode register 6 Port mode register 7 Port mode register 8 Port mode register 9 Note After Reset 00H 00H 00H 00H 00H 00H 00H 00H 00H FFH FFH 00H 00H 00H 00H 0000H 8 Bits - 16 Bits - - - - - - - - - - - - - - - Port register 0 Port register 1 8-bit timer H compare register 00 Port register 3 Port register 4 Port register 6 Port register 7 Port register 8 Port register 9 Receive buffer register 60 Transmit buffer register 60 Port register 12 Port register 13 8-bit timer H compare register 10 Serial I/O shift register 10 16-bit timer counter 00 P0 P1 CMP00 P3 P4 P6 P7 P8 P9 RXB60 TXB60 P12 P13 CMP10 SIO10 TM00 R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R R - - - - - - 16-bit timer capture/compare register 000 CR000 R/W - - 0000H 16-bit timer capture/compare register 010 CR010 R/W - 0000H TM50 CR50 ADCR ADCRH CMP01 CMP11 TM51 PM0 PM1 ADPC PM3 PM4 PM6 PM7 PM8 PM9 ADM ADS R R/W R R R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W - - - - - - - - - - - - - - - - - - - - - - - - 00H 00H 0000H 00H 00H 00H 00H FFH FFH 00H FFH FFH FFH FFH FFH FFH 00H 00H A/D converter mode register Analog input channel specification register Note PD78F0884, 78F0885, 78F0886 only. 60 User's Manual U17555EJ3V0UD www..com CHAPTER 3 CPU ARCHITECTURE Table 3-7. Special Function Register List (2/5) Address Special Function Register (SFR) Name Symbol R/W Manipulatable Bit Unit 1 Bit FF2CH FF2DH FF2EH Port mode register 12 Port mode register 13 Asynchronous serial interface selection register 61 FF2FH Asynchronous serial interface reception error status register 61 FF30H FF31H FF33H FF34H FF37H FF38H Pull-up resistor option register 0 Pull-up resistor option register 1 Pull-up resistor option register 3 Pull-up resistor option register 4 Pull-up resistor option register 7 Asynchronous serial interface transmission status register 61 FF39H FF3AH Clock selection register 61 Asynchronous serial interface Receive buffer register 61 FF3BH Asynchronous serial interface Transmit buffer register 61 FF3CH FF3DH FF3EH FF3FH FF40H FF41H FF42H FF43H FF44H FF45H FF48H FF49H FF4AH FF4BH FF4CH FF4DH FF4FH FF50H Input switch control register Asynchronous serial interface operation mode register 60 FF53H Asynchronous serial interface reception error status register 60 ASIS60 R - - 00H ISC ASIM60 R/W R/W - - 00H 01H Multiplication/Division Data Register A0H MDA0H R/W - 0000H External interrupt rising edge enable register External interrupt falling edge enable register Multiplication/Division Data Register A0L EGP EGN MDA0L Pull-up resistor option register 12 Pull-up resistor option register 13 Note After Reset FFH FEH 01H 8 Bits 16 Bits - - - - - - - - - - - - - - - - - - - - - PM12 PM13 ASIM61 R/W R/W R/W - - - - - - - ASIS61 R 00H PU0 PU1 PU3 PU4 PU7 ASIF61 R/W R/W R/W R/W R/W R 00H 00H 00H 00H 00H 00H CKSR61 RXB61 R/W R/W 00H FFH TXB61 R/W FFH PU12 PU13 BRGC61 ASICL61 CKS CR51 DMUC0 TMC51 R/W R/W R/W R/W R/W R/W R/W R/W 00H 00H FFH 16H 00H 00H 00H 00H 0000H Baud rate generator control register 61 Asynchronous serial interface control register 61 Clock output selection register 8-bit timer compare register 51 Multiplier/divider control register 0 8-bit timer mode control register 51 Multiplier/divider data register 0 SDR0 SDR0L R/W SDR0H R/W R/W R/W - - - 00H 00H 0000H Note PD78F0884, 78F0885, 78F0886 only. User's Manual U17555EJ3V0UD 61 www..com CHAPTER 3 CPU ARCHITECTURE Table 3-7. Special Function Register List (3/5) Address Special Function Register (SFR) Name Symbol R/W Manipulatable Bit Unit 1 Bit FF55H Asynchronous serial interface transmission status register 60 FF56H FF57H FF58H FF60H FF61H FF62H FF63H FF64H FF65H FF66H FF67H FF68H FF69H FF6AH FF6BH FF6EH FF6FH CAN Global Macro Automatic Block Transmission Delay Register Module Last Out Pointer Register 8-bit timer H mode register 0 Timer clock selection register 50 8-bit timer mode control register 50 CAN Global Macro Clock Selection Register CAN Global Macro Automatic Block Transmission Register FF70H FF71H FF72H FF73H FF74H FF75H FF76H FF77H FF78H FF79H FF7AH FF7BH FF7CH FF7DH FF7EH FF7FH FF80H FF81H FF84H Serial operation mode register 10 Serial clock selection register 10 Transmit buffer register 10 CSIM10 CSIC10 SOTB10 R/W R/W R/W - - - - 00H 00H 00H CAN Module Mask 4 Register H C0MASK4H R/W - - Undefined CAN Module Mask 4 Register L C0MASK4L R/W - - Undefined CAN Module Mask 3 Register H C0MASK3H R/W - - Undefined CAN Module Mask 3 Register L C0MASK3L R/W - - Undefined CAN Module Mask 2 Register H C0MASK2H R/W - - Undefined CAN Module Mask 2 Register L C0MASK2L R/W - - Undefined CAN Module Mask 1 Register H C0MASK1H R/W - - Undefined CAN Module Mask 1 Register L C0MASK1L R/W - - Undefined C0LOPT TMHMD0 TCL50 TMC50 C0GMCS C0GMABTD R R/W R/W R/W R/W R/W - - - - - - - - - Undefined 00H 00H 00H 0FH 00H C0GMABT R/W - - 0000H Clock selection register 60 Baud rate generator control register 60 Asynchronous serial interface control register 60 Module Receive History List Get Pointer Register Module Transmission History List Get Pointer Register CAN Global Macro Clock Selection C0GMCTRL R/W - - 0000H C0TGPT R/W - - xx02H CKSR60 BRGC60 ASICL60 C0RGPT R/W R/W R/W R/W - - - - - - - 00H FFH 16H xx02H ASIF60 R - 8 Bits 16 Bits - After Reset 00H 62 User's Manual U17555EJ3V0UD www..com CHAPTER 3 CPU ARCHITECTURE Table 3-7. Special Function Register List (4/5) Address Special Function Register (SFR) Name Symbol R/W Manipulatable Bit Unit 1 Bit FF8AH FF8BH FF8CH FF8FH FF90H FF91H FF92H FF93H FF94H FF95H FF96H FF97H FF98H FF99H FF9BH FF9CH FF9DH FF9EH FF9FH FFA0H FFA1H FFA2H FFA3H FFA4H FFACH FFAEH FFAFH FFB0H FFB1H FFB2H FFB3H FFB4H FFB5H FFB6H FFB7H FFB8H 16-bit timer mode control register 01 Prescaler mode register 01 Capture/compare control register 01 TMC01 PRM01 CRC01 R/W R/W R/W - - - 00H 00H 00H 16-bit timer capture/compare register 011 CR011 R/W - - 0000H 16-bit timer capture/compare register 001 CR001 R/W - - 0000H 16-bit timer counter 01 TM01 CAN Module bit rate Prescaler register CAN Module Last In Pointer Register Internal oscillator mode register Main clock mode register Main OSC control register C0BRP C0LIPT RCM MCM MOC R/W R R/W R/W R/W R R/W R R/W - - - - - - - - - - - - FFH Undefined 00H Note2 After Reset 8 Bits - 16 Bits 0000H CAN module time stamp register C0TS R/W - Timer clock selection register 51 Watch timer operation mode register CAN Module Control Register TCL51 WTM C0CTRL R/W R/W R/W - - - - 00H 00H 0000H CAN Module Last Error Code Register CAN Module Information Register CAN Module Error Counters C0LEC C0INFO C0ERC R/W R R - - - - - - 00H 00H 0000H CAN Module Interrupt Enable Register C0IE R/W - - 0000H CAN Module Interrupt Pending Register C0INTS R/W - - 0000H Watchdog timer enable register CAN Module Bit Rate Register WDTE C0BTR R/W R/W - - - - 1AH/9AH Note1 370FH 00H 80H 00H 05H 00H Note3 Oscillation stabilization time counter status register OSTC Oscillation stabilization time select register Reset control flag register Multiplier/divider data register B0 OSTS RESF MDB0 MDB0L MDB0H 0000H R - - 0000H Notes 1. 2. 3. The reset value of WDTE is determined by setting of option byte. The value of this register is 00H immediately after a reset release but automatically changes to 80H after internal high-speed oscillator oscillation has been stabilized. This value varies depending on the reset source. User's Manual U17555EJ3V0UD 63 www..com CHAPTER 3 CPU ARCHITECTURE Tables 3-7. Special Function Register List (5/5) Address Special Function Register (SFR) Name Symbol R/W Manipulatable Bit Unit 1 Bit FFB9H FFBAH FFBBH FFBCH FFBDH FFBEH FFBFH FFC2H FFC4H FFE0H FFE1H FFE2H FFE3H FFE6H FFE7H FFE8H FFE9H FFEAH FFEBH FFEEH FFEFH FFF0H FFF4H 16-bit timer output control register 01 16-bit timer mode control register 00 Prescaler mode register 00 Capture/compare control register 00 16-bit timer output control register 00 Low-voltage detection register Low-voltage detection level selection register Flash status register Flash programming mode control register Interrupt request flag register 0L Interrupt request flag register 0H Interrupt request flag register 1L Interrupt request flag register 1H Interrupt mask flag register 1L Interrupt mask flag register 1H Priority specification flag register 0L Priority specification flag register 0H Priority specification flag register 1L Priority specification flag register 1H 8-bit timer H carrier control register 1 Clock operation mode select register Internal memory size switching register Internal expansion RAM size switching register FFFAH FFFBH Note2 Note2 After Reset 8 Bits 16 Bits - - - - - - - - - 00H 00H 00H 00H 00H 00H 00H 00H 08H/0CH 00H 00H 00H 00H FFH DFH FFH FFH FFH FFH - - - - - - 00H 00H CFH 0CH Note1 TOC01 TMC00 PRM00 CRC00 TOC00 LVIM LVIS PFS FLPMC IF0 IF0L IF0H IF1 IF1L IF1H MK1 MK1L MK1H PR0 PR0L PR0H PR1 PR1L PR1H TMCYC1 OSCCTL IMS IXS R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W - - 8-bit timer H mode register 1 Processor clock control register TMHMD1 PCC R/W R/W 00H 01H Notes 1. 2. Varies depending on the operation mode. * User mode: 08H * On-board mode: 0CH Regardless of the internal memory capacity, the initial values of the internal memory size switching register (IMS) and internal expansion RAM size switching register (IXS) of the 78K0/FC2 is fixed (IMS = CFH, IXS = 0CH). Therefore, set the value corresponding to each as indicated below. Flash Memory Version IMS C8H CCH CFH 0AH 08H 08H IXS PD78F0881, 78F0884 PD78F0882, 78F0885 PD78F0883, 78F0886 64 User's Manual U17555EJ3V0UD www..com CHAPTER 3 CPU ARCHITECTURE 3.3 Instruction Address Addressing An instruction address is determined by program counter (PC) contents and is normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed. When a branch instruction is executed, the branch destination information is set to the PC and branched by the following addressing (for details of instructions, refer to 78K/0 Series Instructions User's Manual (U12326E). 3.3.1 Relative addressing [Function] The value obtained by adding 8-bit immediate data (displacement value: jdisp8) of an instruction code to the start address of the following instruction is transferred to the program counter (PC) and branched. displacement value is treated as signed two's complement data (-128 to +127) and bit 7 becomes a sign bit. In other words, relative addressing consists of relative branching from the start address of the following instruction to the -128 to +127 range. This function is carried out when the BR $addr16 instruction or a conditional branch instruction is executed. [Illustration] 15 PC + 15 8 7 S jdisp8 15 PC 0 6 0 0 ... PC indicates the start address of the instruction after the BR instruction. The When S = 0, all bits of are 0. When S = 1, all bits of are 1. User's Manual U17555EJ3V0UD 65 www..com CHAPTER 3 CPU ARCHITECTURE 3.3.2 Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) and branched. This function is carried out when the CALL !addr16 or BR !addr16 or CALLF !addr11 instruction is executed. CALL !addr16 and BR !addr16 instructions can be branched to the entire memory space. The CALLF !addr11 instruction is branched to the 0800H to 0FFFH area. [Illustration] In the case of CALL !addr16 and BR !addr16 instructions 7 CALL or BR Low Addr. High Addr. 0 15 PC 87 0 In the case of CALLF !addr11 instruction 76 fa10-8 fa7-0 4 3 CALLF 0 15 PC 0 0 0 0 11 10 1 87 0 66 User's Manual U17555EJ3V0UD www..com CHAPTER 3 CPU ARCHITECTURE 3.3.3 Table indirect addressing [Function] Table contents (branch destination address) of the particular location to be addressed by bits 1 to 5 of the immediate data of an operation code are transferred to the program counter (PC) and branched. This function is carried out when the CALLT [addr5] instruction is executed. This instruction references the address stored in the memory table from 40H to 7FH, and allows branching to the entire memory space. [Illustration] 7 Operation code 1 6 1 5 ta4-0 1 0 1 15 Effective address 0 0 0 0 0 0 0 8 0 7 0 6 1 5 10 0 7 Memory (Table) Low Addr. 0 Effective address+1 High Addr. 15 PC 8 7 0 3.3.4 Register addressing [Function] Register pair (AX) contents to be specified with an instruction word are transferred to the program counter (PC) and branched. This function is carried out when the BR AX instruction is executed. [Illustration] 7 rp A 0 7 X 0 15 PC 8 7 0 User's Manual U17555EJ3V0UD 67 www..com CHAPTER 3 CPU ARCHITECTURE 3.4 Operand Address Addressing The following methods are available to specify the register and memory (addressing) to undergo manipulation during instruction execution. 3.4.1 Implied addressing [Function] The register that functions as an accumulator (A and AX) among the general-purpose registers is automatically (implicitly) addressed. Of the 78K0/FC2 instruction words, the following instructions employ implied addressing. Instruction MULU DIVUW ADJBA/ADJBS ROR4/ROL4 Register to Be Specified by Implied Addressing A register for multiplicand and AX register for product storage AX register for dividend and quotient storage A register for storage of numeric values that become decimal correction targets A register for storage of digit data that undergoes digit rotation [Operand format] Because implied addressing can be automatically employed with an instruction, no particular operand format is necessary. [Description example] In the case of MULU X With an 8-bit x 8-bit multiply instruction, the product of A register and X register is stored in AX. In this example, the A and AX registers are specified by implied addressing. 68 User's Manual U17555EJ3V0UD www..com CHAPTER 3 CPU ARCHITECTURE 3.4.2 Register addressing [Function] The general-purpose register to be specified is accessed as an operand with the register bank select flags (RBS0 to RBS1) and the register specify codes (Rn and RPn) of an operation code. Register addressing is carried out when an instruction with the following operand format is executed. When an 8-bit register is specified, one of the eight registers is specified with 3 bits in the operation code. [Operand format] Identifier r rp Description X, A, C, B, E, D, L, H AX, BC, DE, HL `r' and `rp' can be described by absolute names (R0 to R7 and RP0 to RP3) as well as function names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL). [Description example] MOV A, C; when selecting C register as r Operation code 0 1 1 0 0 0 1 0 Register specify code INCW DE; when selecting DE register pair as rp Operation code 1 0 0 0 0 1 0 0 Register specify code User's Manual U17555EJ3V0UD 69 www..com CHAPTER 3 CPU ARCHITECTURE 3.4.3 Direct addressing [Function] The memory to be manipulated is directly addressed with immediate data in an instruction word becoming an operand address. [Operand format] Identifier addr16 Description Label or 16-bit immediate data [Description example] MOV A, !0FE00H; when setting !addr16 to FE00H Operation code 1 0 0 0 1 1 1 0 OP code 0 0 0 0 0 0 0 0 00H 1 1 1 1 1 1 1 0 FEH [Illustration] 7 OP code addr16 (lower) addr16 (upper) 0 Memory 70 User's Manual U17555EJ3V0UD www..com CHAPTER 3 CPU ARCHITECTURE 3.4.4 Short direct addressing [Function] The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. This addressing is applied to the 256-byte space FE20H to FF1FH. Internal RAM and special function registers (SFRs) are mapped at FE20H to FEFFH and FF00H to FF1FH, respectively. The SFR area (FF00H to FF1FH) where short direct addressing is applied is a part of the overall SFR area. Ports that are frequently accessed in a program and compare and capture registers of the timer/event counter are mapped in this area, allowing SFRs to be manipulated with a small number of bytes and clocks. When 8-bit immediate data is at 20H to FFH, bit 8 of an effective address is set to 0. When it is at 00H to 1FH, bit 8 is set to 1. Refer to the [Illustration] shown below. [Operand format] Identifier saddr saddrp Description Immediate data that indicate label or FE20H to FF1FH Immediate data that indicate label or FE20H to FF1FH (even address only) [Description example] MOV 0FE30H, A; when transferring value of A register to saddr (FE30H) Operation code 1 1 1 1 0 0 1 0 OP code 0 0 1 1 0 0 0 0 30H (saddr-offset) [Illustration] 7 OP code saddr-offset 0 Short direct memory 15 Effective address 1 1 1 1 1 1 1 87 0 When 8-bit immediate data is 20H to FFH, = 0 When 8-bit immediate data is 00H to 1FH, = 1 User's Manual U17555EJ3V0UD 71 www..com CHAPTER 3 CPU ARCHITECTURE 3.4.5 Special function register (SFR) addressing [Function] A memory-mapped special function register (SFR) is addressed with 8-bit immediate data in an instruction word. This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, the SFRs mapped at FF00H to FF1FH can be accessed with short direct addressing. [Operand format] Identifier sfr sfrp Description Special function register name 16-bit manipulatable special function register name (even address only) [Description example] MOV PM0, A; when selecting PM0 (FF20H) as sfr Operation code 1 1 1 1 0 1 1 0 OP code 0 0 1 0 0 0 0 0 20H (sfr-offset) [Illustration] 7 OP code sfr-offset 0 SFR 15 Effective address 1 1 1 1 1 1 1 87 1 0 72 User's Manual U17555EJ3V0UD www..com CHAPTER 3 CPU ARCHITECTURE 3.4.6 Register indirect addressing [Function] Register pair contents specified by a register pair specify code in an instruction word and by a register bank select flag (RBS0 and RBS1) serve as an operand address for addressing the memory. This addressing can be carried out for all the memory spaces. [Operand format] Identifier - [DE], [HL] Description [Description example] MOV A, [DE]; when selecting [DE] as register pair Operation code 1 0 0 0 0 1 0 1 [Illustration] 16 DE D 87 E The memory address specified with the register pair DE 0 7 The contents of the memory addressed are transferred. 7 A 0 Memory 0 User's Manual U17555EJ3V0UD 73 www..com CHAPTER 3 CPU ARCHITECTURE 3.4.7 Based addressing [Function] 8-bit immediate data is added as offset data to the contents of the base register, that is, the HL register pair in the register bank specified by the register bank select flag (RBS0 and RBS1), and the sum is used to address the memory. Addition is performed by expanding the offset data as a positive number to 16 bits. A carry from the 16th bit is ignored. This addressing can be carried out for all the memory spaces. [Operand format] Identifier - [HL + byte] Description [Description example] MOV A, [HL + 10H]; when setting byte to 10H Operation code 1 0 1 0 1 1 1 0 0 0 0 1 0 0 0 0 [Illustration] 16 HL H 87 L +10 0 7 The contents of the memory addressed are transferred. 7 A 0 Memory 0 74 User's Manual U17555EJ3V0UD www..com CHAPTER 3 CPU ARCHITECTURE 3.4.8 Based indexed addressing [Function] The B or C register contents specified in an instruction word are added to the contents of the base register, that is, the HL register pair in the register bank specified by the register bank select flag (RBS0 and RBS1), and the sum is used to address the memory. Addition is performed by expanding the B or C register contents as a positive number to 16 bits. A carry from the 16th bit is ignored. This addressing can be carried out for all the memory spaces. [Operand format] Identifier - [HL + B], [HL + C] Description [Description example] In the case of MOV A, [HL + B]; (selecting B register) Operation code 1 0 1 0 1 0 1 1 [Illustration] 16 HL H + 7 B 0 8 7 L 0 7 The contents of the memory addressed are transferred. 7 A 0 Memory 0 User's Manual U17555EJ3V0UD 75 www..com CHAPTER 3 CPU ARCHITECTURE 3.4.9 Stack addressing [Function] The stack area is indirectly addressed with the stack pointer (SP) contents. This addressing method is automatically employed when the PUSH, POP, subroutine call and return instructions are executed or the register is saved/reset upon generation of an interrupt request. With stack addressing, only the internal high-speed RAM area can be accessed. [Description example] In the case of PUSH DE; (saving DE register) Operation code 1 0 1 1 0 1 0 1 [Illustration] 7 SP FEE0H FEE0H FEDFH SP FEDEH FEDEH D E Memory 0 76 User's Manual U17555EJ3V0UD www..com CHAPTER 4 PORT FUNCTIONS 4.1 Port Functions There are two types of pin I/O buffer power supplies: AVREF, EVDD/VDD. The relationship between these power supplies and the pins is shown below. Table 4-1. Pin I/O Buffer Power Supplies Power Supply AVREF P80 to P87, P90 Note Corresponding Pins EVDD/VDD * Port pins other than P80 to P87, P90 * Non-port pins Note Note P90 is PD78F0884, 78F0885, 78F0886 only. 78K0/FC2 products are provided with the ports shown in Figure 4-1 and 4-2, which enable variety of control operations. In addition to the function as digital I/O ports, these ports have several alternate functions. For details of the alternate functions, refer to CHAPTER 2 PIN FUNCTIONS. PD78F0881, 78F0882, 78F0883 have a total of 37 I/O ports, ports 0, 1, 3, 4, 6 to 8, 12 and 13. The port configuration is shown below. Figure 4-1. Port Types (PD78F0881, 78F0882, 78F0883) P00 P01 P10 P70 Port 7 P73 P80 Port 0 Port 1 Port 8 P17 P30 P87 P120 Port 12 P124 Port 13 P130 P33 P40 P41 P60 Port 6 P62 Port 4 Port 3 User's Manual U17555EJ3V0UD 77 www..com CHAPTER 4 PORT FUNCTIONS PD78F0884, 78F0885, 78F0886 have a total of 41 I/O ports, ports 0, 1, 3, 4, 6 to 9, 12 and 13. The port configuration is shown below. Figure 4-2. Port Types (PD78F0884, 78F0885, 78F0886) P00 P01 P06 P10 P70 Port 7 P73 P80 Port 0 Port 1 Port 8 P17 P87 Port 9 P90 P120 Port 12 P124 Port 13 P130 P131 P33 P40 P41 P60 Port 6 P63 Port 4 P30 Port 3 4.2 Port Configuration Ports include the following hardware. Table 4-2. Port Configuration (PD78F0881, 78F0882, 78F0883) Item Control registers Configuration Port mode register (PM0, PM1, PM3, PM4, PM6 to PM8, PM12, PM13) Port register (P0, P1, P3, P4, P6 to P8, P12, P13) Pull-up resistor option register (PU0, PU1, PU3, PU4, PU7, PU12) Port Pull-up resistor Total: 37 (CMOS I/O: 33, CMOS output: 1, N-ch open drain I/O: 3) Total: 21 Table 4-3. Port Configuration (PD78F0884, 78F0885, 78F0886) Item Control registers Configuration Port mode register (PM0, PM1, PM3, PM6 to PM9, PM12, PM13) Port register (P0, P1, P3, P4 to P9, P12, P13) Pull-up resistor option register (PU0, PU1, PU3, PU4, PU7, PU12, PU13) Port Pull-up resistor Total: 41 (CMOS I/O: 36, CMOS output: 1, N-ch open drain I/O: 4) Total: 23 78 User's Manual U17555EJ3V0UD www..com CHAPTER 4 PORT FUNCTIONS 4.2.1 Port 0 Port 0 is a 3-bit I/O port with an output latch. Port 0 can be set to the input mode or output mode in 1-bit units using port mode register 0 (PM0). When the P00, P01 and P06 pins are used as an input port, use of an on-chip pullup resistor can be specified in 1-bit units by pull-up resistor option register 0 (PU0). This port can also be used for timer I/O. Reset signal generation sets port 0 to input mode. Figures 4-3 and 4-4 show block diagrams of port 0. Caution P06 is PD78F0884, 78F0885, 78F0886 only. Figure 4-3. Block Diagram of P00 EVDD WRPU PU0 PU00 P-ch Alternate function RD Selector Internal bus WRPORT P0 Output latch (P00) WRPM PM0 PM00 P00/TI000 P0: PU0: PM0: RD: Port register 0 Pull-up resistor option register 0 Port mode register 0 Read signal WRxx: Write signal User's Manual U17555EJ3V0UD 79 www..com CHAPTER 4 PORT FUNCTIONS Figure 4-4. Block Diagram of P01 and P06 EVDD WRPU PU0 PU01, PU06 P-ch Alternate function RD Internal bus WRPORT P0 Output latch (P01, P06) WRPM PM0 PM01, PM06 P01/TI010/TO00, P06/TI011/TO01 Alternate function P0: PU0: PM0: RD: Port register 0 Pull-up resistor option register 0 Port mode register 0 Read signal WRxx: Write signal Caution P06 is PD78F0884, 78F0885, 78F0886 only. 80 User's Manual U17555EJ3V0UD Selector www..com CHAPTER 4 PORT FUNCTIONS 4.2.2 Port 1 Port 1 is an 8-bit I/O port with an output latch. Port 1 can be set to the input mode or output mode in 1-bit units using port mode register 1 (PM1). When the P10 to P17 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 1 (PU1). This port can also be used for external interrupt request input, serial interface data I/O, clock I/O, and timer I/O. Reset signal generation sets port 1 to input mode. Figures 4-5 to 4-7 show block diagrams of port 1. EVDD WRPU PU1 PU10, PU16 and PU17 Alternate function RD P-ch Internal bus WRPORT P1 Output latch (P10, P16, P17) WRPM PM1 PM10, PM16 and PM17 P10/SCK10/TxD61, P16/TOH1/INTP5, P17/TI50/TO50 Alternate function P1: PU1: PM1: RD: Port register 1 Pull-up resistor option register 1 Port mode register 1 Read signal WRxx: Write signal Selector User's Manual U17555EJ3V0UD 81 www..com CHAPTER 4 PORT FUNCTIONS Figure 4-6. Block Diagram of P11 and P14 EVDD WRPU PU1 PU11, PU14 P-ch Alternate function RD Internal bus Selector WRPORT P1 Output latch (P11, P14) WRPM PM1 PM11, PM14 P11/SI10/RxD61, P14/RxD60 P1: PU1: PM1: RD: Port register 1 Pull-up resistor option register 1 Port mode register 1 Read signal WRxx: Write signal 82 User's Manual U17555EJ3V0UD www..com CHAPTER 4 PORT FUNCTIONS Figure 4-7. Block Diagram of P12, P13 and P15 EVDD WRPU PU1 PU12, ,PU13 and PU15 RD P-ch Internal bus WRPORT P1 Output latch (P12, PU13, P15) WRPM PM1 PM12, PM13 and PM15 P12/SO10, P13/TxD60, P15/TOH0 Alternate function P1: PU1: PM1: RD: Port register 1 Pull-up resistor option register 1 Port mode register 1 Read signal WRxx: Write signal Selector User's Manual U17555EJ3V0UD 83 www..com CHAPTER 4 PORT FUNCTIONS 4.2.3 Port 3 Port 3 is a 4-bit I/O port with an output latch. Port 3 can be set to the input mode or output mode in 1-bit units using port mode register 3 (PM3). When used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 3 (PU3). This port can also be used for external interrupt request input and timer I/O. Reset signal generation sets port 3 to input mode. Figures 4-8 and 4-9 show block diagrams of port 3. EVDD WRPU PU3 PU30 to PU32 P-ch Alternate function RD Internal bus WRPORT P3 Output latch (P30 to P32) WRPM PM3 PM30 to PM32 P30/INTP1, P31/INTP2, P32/INTP3 P3: PU3: PM3: RD: Port register 3 Pull-up resistor option register 3 Port mode register 3 Read signal WRxx: Write signal 84 User's Manual U17555EJ3V0UD Selector www..com CHAPTER 4 PORT FUNCTIONS Figure 4-9. Block Diagram of P33 EVDD WRPU PU3 PU33 P-ch Alternate function RD Internal bus WRPORT P3 Output latch (P33) WRPM PM3 PM33 P33/INTP4/TI51/TO51 Alternate function P3: PU3: PM3: RD: Port register 3 Pull-up resistor option register 3 Port mode register 3 Read signal WRxx: Write signal Selector User's Manual U17555EJ3V0UD 85 www..com CHAPTER 4 PORT FUNCTIONS 4.2.4 Port 4 Port 4 is a 2-bit I/O port with an output latch. Port 4 can be set to the input mode or output mode in 1-bit units using port mode register 4 (PM4). Use of an on-chip pull-up resistor can be specified in 1-bit units with pull-up resistor option register 4 (PU4). Reset signal generation sets port 4 to input mode. Figure 4-10 shows a block diagram of port 4. Figure 4-10. Block Diagram of P40, P41 EVDD WRPU PU4 PU40, PU41 P-ch RD Internal bus Selector WRPORT P4 Output latch (P40, P41) P40, P41 WRPM PM4 PM40, PM41 P4: PU4: PM4: RD: Port register 4 Pull-up resistor option register 4 Port mode register 4 Read signal WRxx: Write signal 86 User's Manual U17555EJ3V0UD www..com CHAPTER 4 PORT FUNCTIONS 4.2.5 Port 6 Port 6 is a 4-bit I/O port with an output latch. Port 6 can be set to the input mode or output mode in 1-bit units using port mode register 6 (PM6). RD Selector Internal bus WRPORT P6 Output latch (P60 to P63) P60 to P63 WRPM PM6 PM60 to PM63 P6: PM6: RD: Port register 6 Port mode register 6 Read signal WRxx: Write signal User's Manual U17555EJ3V0UD 87 www..com CHAPTER 4 PORT FUNCTIONS 4.2.6 Port 7 Port 7 is a 4-bit I/O port with an output latch. Port 7 can be set to the input mode or output mode in 1-bit units using port mode register 7 (PM7). When the P70 to P73 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 7 (PU7). This port can also be used for external interrupt request input, and clock output pins, buzzer output pins, CAN I/F I/O. Reset signal generation sets port 7 to input mode. Figures 4-12 and 4-13 show block diagrams of port 7. Figure 4-12. Block Diagram of P70 EVDD WRPU PU7 PU70 RD P-ch Internal bus WRPORT P7 Output latch (P70) WRPM PM7 PM70 P70CTxD60 Alternate function P7: PU7: PM7: RD: Port register 7 Pull-up resistor option register 7 Port mode register 7 Read signal WRxx: Write signal 88 User's Manual U17555EJ3V0UD Selector www..com CHAPTER 4 PORT FUNCTIONS Figure 4-13. Block Diagram of P71 EVDD WRPU PU7 PU71 P-ch Alternate function RD Selector Internal bus WRPORT P7 Output latch (P71) WRPM PM7 PM71 P71/CRxD P7: PU7: PM7: RD: Port register 7 Pull-up resistor option register 7 Port mode register 7 Read signal WRxx: Write signal User's Manual U17555EJ3V0UD 89 www..com CHAPTER 4 PORT FUNCTIONS Figure 4-14. Block Diagram of P72 and P73 EVDD WRPU PU7 PU72 and PU73 P-ch Alternate function RD Internal bus WRPORT P7 Output latch (P72 and P73) WRPM PM7 PM72 and PM73 P72/PCL/INTP6 P73/BUZ/INTP7 Alternate function P7: PU7: PM7: RD: Port register 7 Pull-up resistor option register 7 Port mode register 7 Read signal WRxx: Write signal 90 User's Manual U17555EJ3V0UD Selector www..com CHAPTER 4 PORT FUNCTIONS 4.2.7 Port 8 ADPC Digital I/O selection Table 4-4. Setting Functions of P80/ANI0 to P87/ANI7 Pins PM8 Input mode Output mode Analog input selection Input mode Selects ANI. Does not select ANI. Output mode Selects ANI. Does not select ANI. ADS - - P80/ANI0 to P87/ANI7 Pin Digital input Digital output Analog input (to be converted) Analog input (not to be converted) Setting prohibited All P80/ANI0 to P87/ANI7 are set in the analog input mode when the reset signal is generated. Figure 4-15 shows a block diagram of port 8. RD Internal bus WRPORT P8 Output latch (P80 to P87) WRPM PM8 PM80 to PM87 A/D converter P80/ANI0 to P87/ANI7 P8: PM8: RD: Port register 8 Port mode register 8 Read signal WRxx: Write signal Selector User's Manual U17555EJ3V0UD 91 www..com CHAPTER 4 PORT FUNCTIONS ADPC Digital I/O selection PM9 Input mode Output mode Analog input selection Input mode Selects ANI. Does not select ANI. Output mode Selects ANI. Does not select ANI. ADS - - Digital input Digital output Analog input (to be converted) Analog input (not to be converted) Setting prohibited P90/ANI8 All P90/ANI8 are set in the analog input mode when the reset signal is generated. Figure 4-16 shows a block diagram of port 9. Cautions 1. P90 is PD78F0884, 78F0885, 78F0886 only. 2. Make the AVREF pin the same potential as the VDD pin when port 9 is used as a digital port. 3. When using P90/ANI80 in the input mode, not only PM9 (input/output) but also the A/D port configuration register (ADPC) (analog input/digital input)must be set (for details, see 12.3 (5) A/D port configuration register (ADPC)). analog input pin). The reset value of ADPC is 00H (P90/ANI8 is 92 User's Manual U17555EJ3V0UD www..com CHAPTER 4 PORT FUNCTIONS Figure 4-16. Block Diagram of P90 RD Internal bus WRPORT P9 Output latch (P90) WRPM PM9 PM90 A/D converter P90/ANI8 P9: PM9: RD: Port register 9 Port mode register 9 Read signal WRxx: Write signal Selector User's Manual U17555EJ3V0UD 93 www..com CHAPTER 4 PORT FUNCTIONS 4.2.9 Port 12 Port 12 is a 5-bit I/O port with an output latch. Port 12 can be set to the input mode or output mode in 1-bit units using port mode register 12 (PM12). When used as an input port only for P120, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 12 (PU12). This port can also be used for external interrupt input, potential input for external low-voltage detector, connecting resonator for main system clock, connecting resonator for subsystem clock, external clock input for main system clock, external clock input for subsystem clock. Reset signal generation sets port 12 to input mode. Figures 4-17 and 4-18 show block diagrams of port 12. 94 User's Manual U17555EJ3V0UD www..com CHAPTER 4 PORT FUNCTIONS Figure 4-17. Block Diagram of P120 EVDD WRPU PU12 PU120 P-ch Alternate function RD Internal bus Selector WRPORT P12 Output latch (P120) WRPM PM12 PM120 P120/INTP0/EXLVI P12: PU12: PM12: RD: Port register 12 Pull-up resistor option register 12 Port mode register 12 Read signal WRxx: Write signal User's Manual U17555EJ3V0UD 95 www..com CHAPTER 4 PORT FUNCTIONS Figure 4-18. Block Diagram of P121 to P124 OSCCTL OSCSEL/ OSCSELS RD WRPORT P12 Output latch (P122/P124) WRPM PM12 PM122/PM124 P122/X2/EXCLK, P124/XT2/EXCLKS OSCCTL OSCSEL/ OSCSELS Internal bus Selector OSCCTL EXCLK, OSCSEL/ EXCLKS, OSCSELS RD WRPORT P12 Output latch (P121/P123) WRPM PM12 PM121/PM123 P121/X1, P123/XT1 OSCCTL OSCSEL/OSCSELS OSCCTL EXCLK/EXCLKS P12: PU12: PM12: RD: Port register 12 Pull-up resistor option register 12 Port mode register 12 Read signal WRxx: Write signal 96 User's Manual U17555EJ3V0UD Selector www..com CHAPTER 4 PORT FUNCTIONS 4.2.10 Port 13 Port 130 is a 1-bit output-only port. Port 131 is 1-bit I/O port. P131 can be set to the input mode or output mode in 1-bit units using port mode register 13 (PM13). When used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 13 (PU13). Figures 4-19 and 4-20 show block diagrams of port 13. Caution P131 is PD78F0884, 78F0885, 78F0886 only. Figure 4-19. Block Diagram of P130 RD Internal bus WRPORT P13 Output latch (P130) P130 P13: RD: Port register 13 Read signal WRxx: Write signal Remark When reset is effected, P130 outputs a low level. If P130 is set to output a high level before reset is effected, the output signal of P130 can be dummy-output as the CPU reset signal. Reset signal P130 Set by software User's Manual U17555EJ3V0UD 97 www..com CHAPTER 4 PORT FUNCTIONS Figure 4-20. Block Diagram of P131 EVDD WRPU PU13 PU131 P-ch RD Internal bus Selector WRPORT P13 Output latch (P131) P131 WRPM PM13 PM131 P13: PU13: PM13: RD: Port register 13 Pull-up resistor option register 13 Port mode register 13 Read signal WRxx: Write signal Caution P131 is PD78F0884, 78F0885, 78F0886 only. 98 User's Manual U17555EJ3V0UD www..com CHAPTER 4 PORT FUNCTIONS 4.3 Registers Controlling Port Function Port functions are controlled by the following three types of registers. * Port mode registers (PM0, PM1, PM3, PM4, PM6 to PM9, PM12, PM13) * Port registers (P0, P1, P3, P4, P6 to P9, P12, P13) User's Manual U17555EJ3V0UD 99 www..com CHAPTER 4 PORT FUNCTIONS Figure 4-21. Format of Port Mode Register Symbol PM0 7 1 7 PM1 PM17 7 PM3 1 7 PM4 1 7 PM6 1 7 PM7 1 7 PM8 PM87 7 PM9 1 7 PM12 1 7 PM13 1 6 PM06 6 PM16 6 1 6 1 6 1 6 1 6 PM86 6 1 6 1 6 1 Note 5 1 5 PM15 5 1 5 1 5 1 5 1 5 PM85 5 1 5 1 5 1 4 1 4 PM14 4 1 4 1 4 1 4 1 4 PM84 4 1 4 PM124 4 1 3 1 3 PM13 3 PM33 3 1 3 PM63 3 PM73 3 PM83 3 1 3 PM123 3 1 Note 2 1 2 PM12 2 PM32 2 1 2 PM62 2 PM72 2 PM82 2 1 2 PM122 2 1 1 PM01 1 PM11 1 PM31 1 PM41 1 PM61 1 PM71 1 PM81 1 1 1 PM121 1 PM131 Note 0 PM00 0 PM10 0 PM30 0 PM40 0 PM60 0 PM70 0 PM80 0 PM90 0 PM120 0 0 Note Address FF20H After reset FFH R/W R/W FF21H FFH R/W FF23H FFH R/W FF24H FFH R/W FF26H FFH R/W FF27H FFH R/W FF28H FFH R/W FF29H FFH R/W FF2CH FFH R/W FF2DH FEH R/W Note Be sure to clear bit 6 of PM0, bit 3 of PM6, bit 0 of PM9 and bit 1 of PM13 to 1 at PD78F0881, 78F0882, 78F0883. PMmn Pmn pin I/O mode selection (m = 0, 1, 3, 4, 6 to 9, 12, 13; n = 0 to 7) 0 1 Output mode (output buffer on) Input mode (output buffer off) 100 User's Manual U17555EJ3V0UD www..com CHAPTER 4 PORT FUNCTIONS Table 4-6. Settings of Port Mode Register and Output Latch When Using Alternate Function (1/2) Pin Name Alternate Function Function Name P00 P01 TI000 TI010 TO00 P06 TI011 TO01 P10 SCK10 I/O Input Input Output Input Output Input Output TxD61 P11 SI10 RxD61 P12 P13 P14 P15 P16 SO10 TxD60 RxD60 TOH0 TOH1 INTP5 P17 TI50 TO50 P30 P31 P32 P33 INTP1 INTP2 INTP3 INTP4 TI51 TO51 P70 P71 P72 CTxD CRxD PCL INTP6 P73 BUZ INTP7 P80-P87 ANI0-ANI7 ANI8 Output Input Input Output Output Input Output Output Input Input Output Input Input Input Input Input Output Output Input Output Input Output Input Input Input 1 1 0 1 0 1 0 0 1 1 0 0 1 0 0 1 1 0 1 1 1 1 1 0 0 1 0 1 0 1 1 1 x x 0 x 0 x 1 1 x x 0 1 x 0 0 x x 0 x x x x x 0 1 x 0 x 0 x x x PMxx Pxx P90 Caution When using P80/ANI0 to P87/ANI7, P90/ANI8 in the input mode, not only PM8 and PM9 (input/output) but also the A/D port configuration register (ADPC) (analog input/digital input) must be set (for details, see 12.3 (4) Analog input channel specification register (ADS) to (7) Port mode register 9 (PM9)). The reset value of ADPC is 00H (P80/ANI0 to P87/ANI7, P90/ANI8 are all analog input pins). Remark x: Pxx: Don't care Port output latch PMxx: Port mode register User's Manual U17555EJ3V0UD 101 www..com CHAPTER 4 PORT FUNCTIONS Table 4-6. Settings of Port Mode Register and Output Latch When Using Alternate Function (2/2) Pin Name Alternate Function Function Name P120 INTP0 EXLVI P121 P122 X1 X2 EXCLK P123 P124 XT1 XT2 EXCLKS I/O Input Input Input Input Input Input Input Input 1 1 1 1 1 1 1 1 x x x x x x x x PMxx Pxx Remark x: Pxx: Don't care Port output latch PMxx: Port mode register 102 User's Manual U17555EJ3V0UD www..com CHAPTER 4 PORT FUNCTIONS (2) Port registers (P0, P1, P3, P4, P6 to P9, P12, P13) These registers write the data that is output from the chip when data is output from a port. If the data is read in the input mode, the pin level is read. If it is read in the output mode, the value of the output latch is read. These registers can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears these registers to 00H. Caution P9 is PD78F0884, 78F0885, 78F0886 only. Figure 4-22. Format of Port Register Symbol P0 7 0 7 P1 P17 7 P3 0 7 P4 0 7 P6 0 7 P7 0 7 P8 P87 7 P9 0 7 P12 0 7 P13 0 6 P06 6 P16 6 0 6 0 6 0 6 0 6 P86 6 0 6 0 6 0 Note 5 0 5 P15 5 0 5 0 5 0 5 0 5 P85 5 0 5 0 5 0 4 0 4 P14 4 0 4 0 4 0 4 0 4 P84 4 0 4 P124 4 0 3 0 3 P13 3 P33 3 0 3 P63 3 P73 3 P83 3 0 3 P123 3 0 Note 2 0 2 P12 2 P32 2 0 2 P62 2 P72 2 P82 2 0 2 P122 2 0 1 P01 1 P11 1 P31 1 P41 1 P61 1 P71 1 P81 1 0 1 P121 1 P131 Note 0 P00 0 P10 0 P30 0 P40 0 P60 0 P70 0 P80 0 P90 0 P120 0 P130 Note Address FF00H After reset 00H (output latch) R/W R/W FF01H 00H (output latch) R/W FF03H 00H (output latch) R/W FF04H 00H (output latch) R/W FF06H 00H (output latch) R/W FF07H 00H (output latch) R/W FF08H 00H (output latch) R/W FF09H 00H (output latch) R/W FF0CH 00H (output latch) R/W FF0DH 00H (output latch) R/W Note Be sure to clear bit 6 of P0, bit 3 of P6, bit 0 to P9 and bit 1 of P13 to 0 at PD78F0881, 78F0882, 78F0883. Pmn m = 0, 1, 3, 4, 6 to 9, 12, 13; n = 0 to 7 Output data control (in output mode) 0 1 Output 0 Output 1 Input data read (in input mode) Input low level Input high level User's Manual U17555EJ3V0UD 103 www..com CHAPTER 4 PORT FUNCTIONS (3) Pull-up resistor option registers (PU0, PU1, PU3, PU4, PU7, PU12, PU13) These registers specify whether the on-chip pull-up resistors of P00, P01, P06, P10 to P17, P30 to P33, P40, P41, P70 to P73, P120, P131 are to be used or not. On-chip pull-up resistors can be used in 1-bit units only for the bits set to input mode of the pins to which the use of an on-chip pull-up resistor has been specified in PU0, PU1, PU3, PU4, PU7, PU12, and PU13. On-chip pull-up resistors cannot be connected to bits set to output mode and bits used as alternate-function output pins, regardless of the settings of PU0, PU1, PU3, PU4 PU5, PU7, PU12, and PU13. These registers can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears these registers to 00H. Caution PU06 and PU131 are PD78F0884, 78F0885, 78F0886 only. Figure 4-23. Format of Pull-up Resistor Option Register Symbol PU0 7 0 7 PU1 PU17 7 PU3 0 7 PU4 0 7 PU7 0 7 PU12 0 7 PU13 0 6 PU06 6 PU16 6 0 6 0 6 PU76 6 0 6 0 Note 5 0 5 PU15 5 0 5 0 5 PU75 5 0 5 0 4 0 4 PU14 4 0 4 0 4 PU74 4 0 4 0 3 0 3 PU13 3 PU33 3 0 3 PU73 3 0 3 0 2 0 2 PU12 2 PU32 2 0 2 PU72 2 0 2 0 1 PU01 1 PU11 1 PU31 1 PU41 1 PU71 1 0 1 PU131 Note 0 PU00 0 PU10 0 PU30 0 PU40 0 PU70 0 PU120 0 0 Address FF30H After reset 00H R/W R/W FF31H 00H R/W FF33H 00H R/W FF34H 00H R/W FF37H 00H R/W FF3CH 00H R/W FF3DH 00H R/W Note Be sure to clear bit 6 of PU0 and bit 1 of PU13 to 0 at PD78F0881, 78F0882, 78F0883. PUmn PUmn pin on-chip pull-up resistor selection (m = 0, 1, 3, 4, 7, 12, 13, n = 0 to 7) 0 1 On-chip pull-up resistor not connected On-chip pull-up resistor connected 104 User's Manual U17555EJ3V0UD www..com CHAPTER 4 PORT FUNCTIONS (4) A/D port configuration register (ADPC) This register switches the P80/ANI0 to P87/ANI7 and P90/ANI8 pins to digital I/O of port or analog input of A/D converter. ADPC can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Table 4-7. Format of A/D Port Configuration Register (ADPC) ADPC3 ADPC2 ADPC1 ADPC0 Analog input (A)/ digital input (D) switching P90/ANI8 P87/ANI7 P86/ANI6 P85/ANI5 P84/ANI4 P83/ANI3 P82/ANI2 P81/ANI1 P80/ANI0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 A A A A A A A A A D A A A A A A A A D D A A A A A A A D D D A A A A A A D D D D A A A A A D D D D D A A A A D D D D D D A A A D D D D D D D A A D D D D D D D D A D D D D D D D D D Other than above Setting prohibited Cautions 1. Select the port from P80, in case P80/ANI0 to P80/ANI7, P90/ANI8 is used as digital port. 2. Set the channel used for A/D conversion to the input mode by using port mode register 8 (PM8) and port mode register 9 (PM9). 3. If data is written to ADPC, a wait cycle is generated. Do not write data to ADPC when the CPU is operating on the subsystem clock and the peripheral hardware clock is stopped. For details, see CHAPTER 30 CAUTIONS FOR WAIT. User's Manual U17555EJ3V0UD 105 www..com CHAPTER 4 PORT FUNCTIONS 4.4 Port Function Operations Port operations differ depending on whether the input or output mode is set, as shown below. 4.4.1 Writing to I/O port (1) Output mode A value is written to the output latch by a transfer instruction, and the output latch contents are output from the pin. Once data is written to the output latch, it is retained until data is written to the output latch again. The data of the output latch is cleared by reset. (2) Input mode A value is written to the output latch by a transfer instruction, but since the output buffer is off, the pin status does not change. Once data is written to the output latch, it is retained until data is written to the output latch again. 4.4.2 Reading from I/O port (1) Output mode The output latch contents are read by a transfer instruction. The output latch contents do not change. (2) Input mode The pin status is read by a transfer instruction. The output latch contents do not change. 4.4.3 Operations on I/O port (1) Output mode An operation is performed on the output latch contents, and the result is written to the output latch. The output latch contents are output from the pins. Once data is written to the output latch, it is retained until data is written to the output latch again. The data of the output latch is cleared by reset. (2) Input mode The pin level is read and an operation is performed on its contents. The result of the operation is written to the output latch, but since the output buffer is off, the pin status does not change. 106 User's Manual U17555EJ3V0UD www..com CHAPTER 4 PORT FUNCTIONS 4.5 Cautions on 1-Bit Manipulation Instruction for Port Register n (Pn) When a 1-bit manipulation instruction is executed on a port that provides both input and output functions, the output latch value of an input port that is not subject to manipulation may be written in addition to the targeted bit. Therefore, it is recommended to rewrite the output latch when switching a port from input mode to output mode. 1-bit manipulation instruction (set1 P1.0) is executed for P10 bit. P10 Low-level output P11 to P17 Pin status: High level Port 1 output latch 0 0 0 0 0 0 0 0 P10 Low-level output P11 to P17 Pin status: High level Port 1 output latch 1 1 1 1 1 1 1 1 1-bit manipulation instruction for P10 bit <1> Port register 1 (P1) is read in 8-bit units. * In the case of P10, an output port, the value of the port output latch (0) is read. * In the case of P11 to P17, input ports, the pin status (1) is read. <2> Set the P10 bit to 1. <3> Write the results of <2> to the output latch of port register 1 (P1) in 8-bit units. User's Manual U17555EJ3V0UD 107 www..com CHAPTER 5 CLOCK GENERATOR 5.1 Functions of Clock Generator The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following system clocks and clock oscillators are selectable. (1) Main system clock <1> X1 oscillator This circuit oscillates a clock of fX = 4 to 20 MHz. Oscillation can be stopped by executing the STOP instruction or using the main OSC control register (MOC). <2> Internal high-speed oscillator This circuit oscillates a clock of fRH = 8 MHz (TYP.). After a RESET release, the CPU always starts operating with this internal high-speed oscillation clock. Oscillation can be stopped by executing the STOP instruction or using the internal oscillator mode register (RCM). An external main system clock (fEXCLK = 4 to 20 MHz) can also be supplied from the EXCLK pin. As the main system clock, a high-speed system clock (X1 clock or external main system clock) or internal high-speed oscillation clock can be selected by using the main clock mode register (MCM). (2) Subsystem clock * Subsystem clock oscillator This circuit oscillates at a frequency of fXT = 32.768 kHz. Oscillation can be stopped by using the processor clock control register (PCC) and clock operation mode select register (OSCCTL). An external subsystem clock (fEXCLKS = 32.768 kHz) can also be supplied from the EXCLKS pin. (3) Internal low-speed oscillation clock (clock for watchdog timer) * Internal low-speed oscillator This circuit oscillates a clock of fRL = 240 kHz (TYP.). After a RESET release, the internal low-speed oscillation clock always starts operating. Oscillation can be stopped by using the internal oscillator mode register (RCM). The internal low-speed oscillation clock cannot be used as the CPU clock. The following hardware operates with the internal low-speed oscillation clock. * Watchdog timer * TMH1 (fRL, fRL/27, fRL/29) Remarks 1. 2. 3. 4. 5. 6. fX: fRH: fXT: fRL: X1 clock oscillation frequency Internal high-speed oscillation clock frequency XT1 clock oscillation frequency Internal low-speed oscillation clock frequency fEXCLK: External main system clock frequency fEXCLKS: External subsystem clock frequency 108 User's Manual U17555EJ3V0UD www..com CHAPTER 5 CLOCK GENERATOR 5.2 Configuration of Clock Generator The clock generator includes the following hardware. Table 5-1. Configuration of Clock Generator Item Control registers Configuration Processor clock control register (PCC) Internal oscillator mode register (RCM) Main clock mode register (MCM) Main OSC control register (MOC) Clock operation mode select register (OSCCTL) Oscillation stabilization time counter status register (OSTC) Oscillation stabilization time select register (OSTS) X1 oscillator XT1 oscillator Internal high-speed oscillator Internal low-speed oscillator Oscillators User's Manual U17555EJ3V0UD 109 www..com Selector 110 Clock operation mode select register (OSCCTL) AMPH EXCLK OSCSEL Main OSC control register (MOC) MSTOP High-speed system clock oscillator X1/P121 X2/EXCLK/ P122 Crystal/ceramic oscillation External input clock fX fXH Figure 5-1. Block Diagram of Clock Generator Internal bus Main clock mode register (MCM) MCS Oscillation stabilization time select register (OSTS) OSTS2 OSTS1 OSTS0 3 Main clock mode register (MCM) XSEL MCM0 Processor clock control register (PCC) CLS CSS PCC2 PCC1 PCC0 4 STOP X1 oscillation stabilization time counter Oscillation stabilization MOST MOST MOST MOST MOST time counter 11 13 14 15 16 status register (OSTC) Peripheral hardware clock switch Controller Peripheral hardware clock (fPRS) CHAPTER 5 CLOCK GENERATOR User's Manual U17555EJ3V0UD fEXCLK Internal high-speed fRH oscillator (8 MHz (TYP.)) Main system fXP clock switch fXP 2 Prescaler fXP 22 fXP 23 fXP 24 CPU clock (fCPU) Subsystem clock oscillator XT1/P123 XT2/EXCLKS/ P124 Crystal oscillation External input clock fXT 1/2 fSUB 2 fSUB Watch timer Internal low-speed fRL oscillator (240 kHz (TYP.)) Watchdog timer, 8-bit timer H1 fEXCLKS EXCLKS OSCSELS Clock operation mode select register (OSCCTL) Internal bus RSTS LSRSTOP RSTOP Option byte 1: Cannot be stopped 0: Can be stopped Internal oscillator mode register (RCM) www..com CHAPTER 5 CLOCK GENERATOR Remarks 1. 2. 3. 4. 5. 6. 7. 8. 9. fX: fRH: fXH: fXP: fPRS: fCPU: fXT: X1 clock oscillation frequency Internal high-speed oscillation clock frequency High-speed system clock oscillation frequency Main system clock oscillation frequency Peripheral hardware clock frequency CPU clock oscillation frequency XT1 clock oscillation frequency Subsystem clock frequency Internal low-speed oscillation clock frequency fEXCLK: External main system clock frequency fEXCLKS: External subsystem clock frequency 10. fSUB: 11. fRL: 5.3 Registers Controlling Clock Generator The following seven registers are used to control the clock generator. * Processor clock control register (PCC) * Internal oscillator mode register (RCM) * Main clock mode register (MCM) * Main OSC control register (MOC) * Clock operation mode select register (OSCCTL) * Oscillation stabilization time counter status register (OSTC) * Oscillation stabilization time select register (OSTS) (1) Processor clock control register (PCC) This register is used to select the CPU clock and the division ratio. PCC is set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets PCC to 01H. User's Manual U17555EJ3V0UD 111 www..com CHAPTER 5 CLOCK GENERATOR Figure 5-2. Format of Processor Clock Control Register (PCC) Address: FFFBH Symbol PCC 7 0 CLS 0 1 CSS Note 2 After reset: 01H 6 0 R/W Note 1 <5> CLS <4> CSS 3 0 CPU clock status 2 PCC2 1 PCC1 0 PCC0 Main system clock Subsystem clock PCC2 0 0 0 0 1 PCC1 0 0 1 1 0 0 0 1 1 0 PCC0 0 1 0 1 0 0 1 0 1 0 Setting prohibited fXP fXP/2 (default) fXP/2 fXP/2 fXP/2 2 3 CPU clock (fCPU) selection 0 4 1 0 0 0 0 1 fSUB/2 Other than above Notes 1. Bit 5 is read-only. 2. Be sure to switch CSS from 1 to 0 when bits 1 (MCS) and 0 (MCM0) of the main clock mode register (MCM) are 1. Caution Be sure to clear bits 3 and 6 to 0. Main system clock oscillation frequency Remarks 1. fXP: 2. fSUB: Subsystem clock frequency The fastest instruction can be executed in 2 clocks of the CPU clock in the 78K0/FC2. Therefore, the relationship between the CPU clock (fCPU) and the minimum instruction execution time is as shown in Table 5-2. Table 5-2. Relationship Between CPU Clock and Minimum Instruction Execution Time CPU Clock (fCPU) Minimum Instruction Execution Time: 2/fCPU High-Speed System Clock At 10 MHz Operation fXP fXP/2 fXP/2 fXP/2 fXP/2 2 3 4 Note High-Speed Internal Note Oscillator Clock At 8 MHz (TYP.) Operation 0.25 s (TYP.) 0.5 s (TYP.) 1.0 s (TYP.) 2.0 s (TYP.) 4.0 s (TYP.) - Subsystem Clock At 32.768 kHz Operation - - - - - 122.1 s At 20 MHz Operation 0.1 s 0.2 s 0.4 s 0.8 s 1.6 s - 0.2 s 0.4 s 0.8 s 1.6 s 3.2 s fSUB/2 Note The main clock mode register (MCM) is used to set the CPU clock (high-speed system clock/internal high-speed oscillation clock) (see Figure 5-4). 112 User's Manual U17555EJ3V0UD www..com CHAPTER 5 CLOCK GENERATOR (2) Internal oscillator mode register (RCM) This register sets the operation mode of internal oscillator. RCM can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to 80HNote 1. Figure 5-3. Format of Internal Oscillator Mode Register (RCM) Address: FFA0H Symbol RCM After reset: 80H <7> RSTS 6 0 Note 1 R/W 5 0 Note 2 4 0 3 0 2 0 <1> LSRSTOP <0> RSTOP RSTS 0 Status of internal high-speed oscillator oscillation Waiting for stabilization of internal high-speed oscillator oscillation in high-accuracy mode (internal high-speed oscillator operation in low-accuracy mode) 1 Internal high-speed oscillator operation in high-accuracy mode LSRSTOP 0 1 Internal low-speed oscillator oscillating/stopped Internal low-speed oscillator oscillating Internal low-speed oscillator stopped RSTOP 0 1 Internal high-speed oscillator oscillating/stopped Internal high-speed oscillator oscillating Internal high-speed oscillator stopped Notes 1. The value of this register is 00H immediately after a reset release but automatically changes to 80H after internal high-speed oscillator oscillation has been stabilized. 2. Bit 7 is read-only. Caution When setting RSTOP to 1, be sure to confirm that the CPU operates with a clock other than the internal high-speed oscillation clock. Specifically, set RSTOP to 1 under either of the following conditions. * When MCS = 1 (when CPU operates with the high-speed system clock) * When CLS = 1 (when CPU operates with the subsystem clock) User's Manual U17555EJ3V0UD 113 www..com CHAPTER 5 CLOCK GENERATOR (3) Main clock mode register (MCM) This register selects the main system clock supplied to CPU clock and clock supplied to peripheral hardware clock. MCM can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 5-4. Format of Main Clock Mode Register (MCM) Address: FFA1H Symbol MCM 7 0 After reset: 00H 6 0 R/W Note 5 0 4 0 3 0 <2> XSEL <1> MCS <0> MCM0 XSEL MCM0 Selection of clock supplied to main system clock and peripheral hardware Main system clock (fXP) Peripheral hardware clock (fPRS) Internal high-speed oscillation clock (fRH) High-speed system clock (fXH) High-speed system clock (fXH) 0 0 1 1 0 1 0 1 Internal high-speed oscillation clock (fRH) MCS 0 1 Main system clock status Operates with internal high-speed oscillation clock Operates with high-speed system clock Note Bit 1 is read-only. Cautions 1. XSEL can be changed only once after a reset release. 2. The peripheral hardware cannot operate when the peripheral hardware clock is stopped. To resume the operation of the peripheral hardware after the peripheral hardware clock has been stopped, initialize the peripheral hardware. 3. A clock other than fPRS is supplied to the following peripheral functions regardless of the setting of XSEL and MCM0. * Watchdog timer * When "fRL/27" is selected as the count clock for 8-bit timer H1 * Peripheral hardware selects the external clock as the clock source (Except when the external count clock of TM0n (n = 0, 1) is selected (TI00n pin valid edge)) 4. It takes one clock to change the CPU clock. 114 User's Manual U17555EJ3V0UD www..com CHAPTER 5 CLOCK GENERATOR (4) Main OSC control register (MOC) This register selects the operation mode of the high-speed system clock. This register is used to stop the X1 oscillator or to disable an external clock input from the EXCLK pin when the CPU operates with a clock other than the high-speed system clock. MOC can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to 80H. Figure 5-5. Format of Main OSC Control Register (MOC) Address: FFA2H Symbol MOC After reset: 80H <7> MSTOP 6 0 R/W 5 0 4 0 3 0 2 0 1 0 0 0 MSTOP Control of high-speed system clock operation X1 oscillation mode External clock input mode External clock from EXCLK pin is enabled External clock from EXCLK pin is disabled 0 1 X1 oscillator operating X1 oscillator stopped Cautions 1. When setting MSTOP to 1, be sure to confirm that the CPU operates with a clock other than the high-speed system clock. Specifically, set MSTOP to 1 under either of the following conditions. * When MCS = 0 (when CPU operates with the internal high-speed oscillation clock) * When CLS = 1 (when CPU operates with the subsystem clock) User's Manual U17555EJ3V0UD 115 www..com CHAPTER 5 CLOCK GENERATOR (5) Clock operation mode select register (OSCCTL) This register selects the operation modes of the high-speed system and subsystem clocks. OSCCTL can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 5-6. Format of Clock Operation Mode Select Register (OSCCTL) Address: FFEFH Symbol OSCCTL After reset: 00H <6> OSCSEL OSCSEL 0 1 0 1 R/W <5> EXCLKS <4> OSCSELS 3 0 P121/X1 pin I/O port Crystal/ceramic resonator connection I/O port I/O port External clock input 2 0 1 0 <0> AMPH <7> EXCLK EXCLK 0 0 1 1 High-speed system clock operation mode I/O port mode X1 oscillation mode I/O port mode External clock input mode Subsystem clock operation mode I/O port mode XT1 oscillation mode I/O port mode External clock input mode P122/X2/EXCLK pin EXCLKS 0 0 1 1 OSCSELS 0 1 0 1 P123/XT1 pin I/O port P124/XT2/EXCLKS pin Crystal resonator connection I/O port I/O port External clock input AMPH 0 1 4 MHz fXH 10 MHz 10 MHz < fXH 20 MHz Operating frequency control Cautions 1. Be sure to set AMPH to 1 if the high-speed system clock oscillation frequency exceeds 10 MHz. 116 User's Manual U17555EJ3V0UD www..com CHAPTER 5 CLOCK GENERATOR Cautions 5. To change the value of EXCLK and OSCSEL, be sure to confirm that bit 7 (MSTOP) of the main OSC control register (MOC) is 1 (the X1 oscillator stops or the external clock from the EXCLK pin is disabled). 6. To change the value of EXCLKS and OSCSELS, confirm that bit 5 (CLS) of the processor clock control register (PCC) is 0 (the CPU is operating with the highspeed system clock). Remark fXH: High-speed system clock oscillation frequency User's Manual U17555EJ3V0UD 117 www..com CHAPTER 5 CLOCK GENERATOR (6) Oscillation stabilization time counter status register (OSTC) This is the status register of the X1 clock oscillation stabilization time counter. checked. OSTC can be read by a 1-bit or 8-bit memory manipulation instruction. When reset is released (reset by RESET input, POC, LVI, and WDT), the STOP instruction and MSTOP (bit 7 of MOC register) = 1 clear OSTC to 00H. Figure 5-7. Format of Oscillation Stabilization Time Counter Status Register (OSTC) Address: FFA3H Symbol OSTC 7 0 After reset: 00H 6 0 R 5 0 4 MOST11 3 MOST13 2 MOST14 1 MOST15 0 MOST16 If the internal high-speed oscillation clock or subsystem clock is used as the CPU clock, the X1 clock oscillation stabilization time can be MOST11 MOST13 MOST14 MOST15 MOST16 Oscillation stabilization time status fX = 10 MHz fX = 20 MHz 1 1 1 1 1 0 1 1 1 1 0 0 1 1 1 0 0 0 1 1 0 0 0 0 1 2 /fX min. 2 /fX min. 2 /fX min. 2 /fX min. 2 /fX min. 16 15 14 13 11 204.8 s min. 102.4 s min. 819.2 s min. 409.6 s min. 1.64 ms min. 819.2 s min. 3.27 ms min. 1.64 ms min. 6.55 ms min. 3.27 ms min. Cautions 1. After the above time has elapsed, the bits are set to 1 in order from MOST11 and remain 1. 2. If the STOP mode is entered and then released while the internal high-speed oscillation clock or subsystem clock is being used as the CPU clock, set the oscillation stabilization time as follows. * Desired OSTC oscillation stabilization time Oscillation stabilization time set by OSTS The oscillation stabilization time counter counts up to the oscillation stabilization time set by OSTS. Note, therefore, that only the status up to the oscillation stabilization time set by OSTS is set to OSTC after STOP mode is released. 3. The X1 clock oscillation stabilization wait time does not include the time until clock oscillation starts ("a" below). STOP mode release X1 pin voltage waveform a Remark fX: X1 clock oscillation frequency 118 User's Manual U17555EJ3V0UD www..com CHAPTER 5 CLOCK GENERATOR (7) Oscillation stabilization time select register (OSTS) This register is used to select the X1 clock oscillation stabilization wait time when the STOP mode is released. The wait time set by OSTS is valid only after the STOP mode is released with the X1 clock selected as the CPU clock. After the STOP mode is released with the internal high-speed oscillation clock or subsystem clock selected as the CPU clock, the oscillation stabilization time must be confirmed by OSTC. OSTS can be set by an 8-bit memory manipulation instruction. Reset signal generation sets OSTS to 05H. Figure 5-8. Format of Oscillation Stabilization Time Select Register (OSTS) Address: FFA4H Symbol OSTS 7 0 After reset: 05H 6 0 R/W 5 0 4 0 3 0 2 OSTS2 1 OSTS1 0 OSTS0 OSTS2 OSTS1 OSTS0 Oscillation stabilization time selection fX = 10 MHz fX = 20 MHz 102.4 s 409.6 s 819.2 s 1.64 ms 3.27 ms 0 0 0 1 1 0 1 1 0 0 Other than above 1 0 1 0 1 2 /fX 2 /fX 2 /fX 2 /fX 2 /fX Setting prohibited 16 15 14 13 11 204.8 s 819.2 s 1.64 ms 3.27 ms 6.55 ms Cautions 1. To set the STOP mode when the X1 clock is used as the CPU clock, set OSTS before executing the STOP instruction. 2. Do not change the value of the OSTS register during the X1 clock oscillation stabilization time. 3. If the STOP mode is entered and then released while the internal high-speed oscillation clock or subsystem clock is being used as the CPU clock, set the oscillation stabilization time as follows. * Desired OSTC oscillation stabilization time Oscillation stabilization time set by OSTS The oscillation stabilization time counter counts up to the oscillation stabilization time set by OSTS. Note, therefore, that only the status up to the oscillation stabilization time set by OSTS is set to OSTC after STOP mode is released. 4. The X1 clock oscillation stabilization wait time does not include the time until clock oscillation starts ("a" below). STOP mode release X1 pin voltage waveform a Remark fX: X1 clock oscillation frequency User's Manual U17555EJ3V0UD 119 www..com CHAPTER 5 CLOCK GENERATOR 5.4 System Clock Oscillator 5.4.1 X1 oscillator The X1 oscillator oscillates with a crystal resonator or ceramic resonator (4 to 20 MHz) connected to the X1 and X2 pins. VSS X1 X2 Crystal resonator or ceramic resonator External clock EXCLK Cautions are listed on the next page. 5.4.2 XT1 oscillator The XT1 oscillator oscillates with a crystal resonator (standard: 32.768 kHz) connected to the XT1 and XT2 pins. VSS XT1 32.768 kHz XT2 External clock EXCLKS Cautions are listed on the next page. 120 User's Manual U17555EJ3V0UD www..com CHAPTER 5 CLOCK GENERATOR Caution When using the X1 oscillator and XT1 oscillator, wire as follows in the area enclosed by the broken lines in the Figures 5-9 and 5-10 to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. Note that the XT1 oscillator is designed as a low-amplitude circuit for reducing power consumption. Figure 5-11 shows examples of incorrect resonator connection. Figure 5-11. Examples of Incorrect Resonator Connection (1/2) (a) Too long wiring (b) Crossed signal line PORT VSS X1 X2 VSS X1 X2 Remark When using the subsystem clock, replace X1 and X2 with XT1 and XT2, respectively. Also, insert resistors in series on the XT2 side. User's Manual U17555EJ3V0UD 121 www..com CHAPTER 5 CLOCK GENERATOR Figure 5-11. Examples of Incorrect Resonator Connection (2/2) (c) Wiring near high alternating current (d) Current flowing through ground line of oscillator (potential at points A, B, and C fluctuates) VDD Pmn VSS X1 X2 High current VSS X1 X2 A B High current C (e) Signals are fetched VSS X1 X2 Remark When using the subsystem clock, replace X1 and X2 with XT1 and XT2, respectively. Also, insert resistors in series on the XT2 side. Caution When X2 and XT1 are wired in parallel, the crosstalk noise of X2 may increase with XT1, resulting in malfunctioning. 122 User's Manual U17555EJ3V0UD www..com CHAPTER 5 CLOCK GENERATOR 5.4.3 When subsystem clock is not used Output (PM123/PM124 = 0): Leave open. PM123, PM124: Bits 3 and 4 of port mode register 12 (PM12) 5.4.4 Internal high-speed oscillator The internal high-speed oscillator is incorporated in the 78K0/FC2. Oscillation can be controlled by the internal oscillator mode register (RCM). After a RESET release, the internal high-speed oscillation clock starts oscillation (8 MHz (TYP.)). 5.4.5 Internal low-speed oscillator The internal low-speed oscillator is incorporated in the 78K0/FC2. The internal low-speed oscillator oscillation clock is only used as the watchdog timer and the clock of 8-bit timer H1. The internal low-speed oscillation clock cannot be used as the CPU clock. "Can be stopped by software" or "Cannot be stopped" can be selected by the option byte. When "Can be stopped by software" is set, oscillation can be controlled by the internal oscillator mode register (RCM). After a RESET release, the internal low-speed oscillation clock starts oscillation and the watchdog timer is operated (240 kHz (TYP.)). 5.4.6 Prescaler The prescaler generates various clocks by dividing the main system clock when the main system clock is selected as the clock to be supplied to the CPU. User's Manual U17555EJ3V0UD 123 www..com CHAPTER 5 CLOCK GENERATOR 5.5 Clock Generator Operation The clock generator generates the following clocks and controls the operation modes of the CPU, such as standby mode. * Main system clock fXP * High-speed system clock fXH X1 clock fX External main system clock fEXCLK * Internal high-speed oscillation clock fRH * Subsystem clock fSUB * XT1 clock fXT * External subsystem clock fEXCLKS * Internal low-speed oscillation clock fRL * CPU clock fCPU * Peripheral hardware clock fPRS The CPU starts operation when the on-chip internal high-speed oscillator starts outputting after a reset release in the 78K0/FC2, thus enabling the following. (1) Enhancement of security function When the X1 clock is set as the CPU clock by the default setting, the device cannot operate if the X1 clock is damaged or badly connected and therefore does not operate after reset is released. However, the start clock of the CPU is the on-chip internal high-speed oscillation clock, so the device can be started by the internal highspeed oscillation clock after a reset release. Consequently, the system can be safely shut down by performing a minimum operation, such as acknowledging a reset source by software or performing safety processing when there is a malfunction. (2) Improvement of performance Because the CPU can be started without waiting for the X1 clock oscillation stabilization time, the total performance can be improved. A timing diagram of the CPU default start using the internal high-speed oscillation clock is shown in Figure 5-12 and 5-13. 124 User's Manual U17555EJ3V0UD www..com CHAPTER 5 CLOCK GENERATOR Figure 5-12 Operation of the clock generating circuit when power supply voltage injection (When 1.59 V POC mode setup (option byte: LVISTART = 0)) Power supply voltage (VDD) 1.8 V 1.59 V (TYP.) 0.5 V/ms (MIN.) 0V Internal reset signal <1> <3> Waiting for voltage stabilization (1.93 to 5.39 ms) Reset processing (11 to 45 s) <5> Internal high-speed oscillation clock Switched by software High-speed system clock <5> Subsystem clock CPU clock <2> Internal high-speed oscillation clock (fRH) Note 1 <4> High-speed system clock (fXH) (when X1 oscillation selected) Subsystem clock (fSUB) (when XT1 oscillation selected) X1 clock oscillation stabilization time: 211/fX to 216/fXNote 2 Starting X1 oscillation <4> is set by software. Starting XT1 oscillation is set by software. <1> The internal reset signal by the power-on clear (POC) circuit is generated after a power supply injection. <2> If power supply voltage exceeds 1.59 V (TYP.), reset will be released and the oscillation start of the highspeed oscillator will be carried out automatically. <3> If power supply voltage is rose by inclination of 0.5 V/ms (MAX.), after the voltage stable waiting time of a power supply/regulator passed after reset release and reset processing will be performed, CPU carries out a start of operation with high-speed oscillation clock . <4> One clock or XT1 clock should set up an oscillation start by software (see (1) in 5.6.1 Controlling highspeed system clock and (1) in 5.6.3 Example of controlling subsystem clock). <5> When you change CPU to X1 clock or XT1 clock, set up a change by software after the oscillation stability waiting of a clock (see (3) in 5.6.1 Controlling high-speed system clock and (3) in 5.6.3 Example of controlling subsystem clock). User's Manual U17555EJ3V0UD 125 www..com CHAPTER 5 CLOCK GENERATOR Cautions 1. When the standup of voltage until it reaches 1.8 V from the time of a power supply injection is looser than 0.5 V/ms (MAX.), input a low level into RESET pin, or set up 2.7 V/1.59 V POC mode (LVISTART = 1) from an option byte until it reaches 1.8 V from the time of a power supply injection (refer to Figure 5-13). When a low level is inputted into RESET pin until it reaches 1.8 V, after the reset release by RESET pin operates to the same timing as <2> of Figure 5-12 or subsequent ones. 2. When using the external clock input from EXCLK pin and EXCLKS pin, oscillation stable waiting time is unnecessary. Remark The clock which is not used as a CPU clock can be suspended by setup of software during microcomputer operation. Moreover, high-speed oscillation clock and a high-speed system clock can suspend a clock by execution of a STOP command (see (4) in 5.6.1 Controlling high-speed system clock, (3) in 5.6.2 Example of controlling internal high-speed oscillation clock, and (4) in 5.6.3 Example of controlling subsystem clock). 126 User's Manual U17555EJ3V0UD www..com CHAPTER 5 CLOCK GENERATOR Figure 5-13 Operation of the clock generating circuit when power supply voltage injection (When 2.7 V/1.59V POC mode setup (option byte: LVISTART = 1)) 2.7 V (TYP.) Power supply voltage (VDD) 0V Internal reset signal <1> <3> Reset processing (11 to 45 s) <5> CPU clock <2> Internal high-speed oscillation clock (fRH) High-speed system clock (fXH) (when X1 oscillation selected) Waiting for oscillation accuracy <4> stabilization (86 to 361 s) X1 clock oscillation stabilization time: 11 2 /fX to 216/fXNote Starting X1 oscillation <4> is set by software. Internal high-speed oscillation clock Switched by software High-speed system clock <5> Subsystem clock Subsystem clock (fSUB) (when XT1 oscillation selected) Starting XT1 oscillation is set by software. <1> The internal reset signal by the power-on clear (POC) circuit is generated after a power supply injection. <2> If power supply voltage exceeds 1.59 V (TYP.), reset will be canceled and the oscillation start of the highspeed oscillator will be carried out automatically. <3> After reset release, after reset processing is performed, CPU carries out a start of operation with high-speed oscillation clock. <4> X1 clock or XT1 clock should set up an oscillation start by software (see (1) in 5.6.1 Controlling highspeed system clock and (1) in 5.6.3 Example of controlling subsystem clock). <5> When you change CPU to X1 clock or XT1 clock, set up a change by software after the oscillation stability waiting of a clock (see (3) in 5.6.1 Controlling high-speed system clock and (3) in 5.6.3 Example of controlling subsystem clock). Note Check the oscillation stable time of X1 clock with an oscillation stable time counter status register (OSTC) when STOP mode release in case the time of reset release (figure 5-13) and a CPU clock are high-speed oscillation clocks . Moreover, when a CPU clock is a high-speed system clock (X1 oscillation), set up the oscillation stable time at the time of STOP mode release by the oscillation stable time selection register (OSTS). User's Manual U17555EJ3V0UD 127 www..com CHAPTER 5 CLOCK GENERATOR Remark The clock which is not used as a CPU clock can be suspended by setup of software during microcomputer operation. Moreover, high-speed oscillation clock and a high-speed system clock can suspend a clock by execution of a STOP command (see (4) in 5.6.1 Controlling high-speed system clock, (3) in 5.6.2 Example of controlling internal high-speed oscillation clock, and (4) in 5.6.3 Example of controlling subsystem clock). 5.6 Controlling Clock * External main system clock: External clock is input to the EXCLK pin. When the high-speed system clock is not used, the X1/P121 and X2/EXCLK/P122 pins can be used as I/O port pins. Caution The X1/P121 and X2/EXCLK/P122 pins are in the I/O port mode after a reset release. The following describes examples of setting procedures for the following cases. (1) When oscillating X1 clock (2) When using external main system clock (3) When using high-speed system clock as CPU clock and peripheral hardware clock (4) When stopping high-speed system clock (1) Example of setting procedure when oscillating the X1 clock <1> Setting frequency (OSCCTL register) Using AMPH, set the gain of the on-chip oscillator according to the frequency to be used. AMPH 0 1 Note Operating Frequency Control 4 MHz fXH 10 MHz 10 MHz < fXH 20 MHz Note Set AMPH before setting the peripheral functions after a reset release. The value of AMPH can be changed only once after a reset release. When AMPH is set to 1, the clock supply to the CPU is stopped for 4.06 to 16.12 s. Remark fXH: High-speed system clock oscillation frequency <2> Setting P121/X1 and P122/X2/EXCLK pins and selecting X1 clock or external clock (OSCCTL register) When EXCLK is cleared to 0 and OSCSEL is set to 1, the mode is switched from port mode to X1 oscillation mode. EXCLK 0 OSCSEL 1 Operation Mode of HighSpeed System Clock Pin X1 oscillation mode Crystal/ceramic resonator connection P121/X1 Pin P122/X2/EXCLK Pin <3> Controlling oscillation of X1 clock (MOC register) If MSTOP is cleared to 0, the X1 oscillator starts oscillating. 128 User's Manual U17555EJ3V0UD www..com CHAPTER 5 CLOCK GENERATOR <4> Waiting for the stabilization of the oscillation of X1 clock Check the OSTC register and wait for the necessary time. During the wait time, other software processing can be executed with the internal high-speed oscillation clock. Cautions 1. Do not change the value of EXCLK and OSCSEL while the X1 clock is operating. 2. Set the X1 clock after the supply voltage has reached the operable voltage of the clock to be used (see CHAPTER 26 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) or CHAPTER 27 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS)). (2) Example of setting procedure when using the external main system clock <1> Setting frequency (OSCCTL register) AMPH 0 1 Note Operating Frequency Control 4 MHz fXH 10 MHz 10 MHz < fXH 20 MHz Note Set AMPH before setting the peripheral functions after a reset release. The value of AMPH can be changed only once after a reset release. The clock supply to the CPU is stopped for the duration of 160 external clocks after AMPH is set to 1. Remark fXH: High-speed system clock oscillation frequency <2> Setting P121/X1 and P122/X2/EXCLK pins and selecting operation mode (OSCCTL register) When EXCLK and OSCSEL are set to 1, the mode is switched from port mode to external clock input mode. EXCLK 1 OSCSEL 1 Operation Mode of HighSpeed System Clock Pin External clock input mode I/O port External clock input P121/X1 Pin P122/X2/EXCLK Pin <3> Controlling external main system clock input (MOC register) When MSTOP is cleared to 0, the input of the external main system clock is enabled. Cautions 1. Do not change the value of EXCLK and OSCSEL while the external main system clock is operating. 2. Set the external main system clock after the supply voltage has reached the operable voltage of the clock to be used (see CHAPTER 26 PRODUCTS)). (3) Example of setting procedure when using high-speed system clock as CPU clock and peripheral hardware clock <1> Setting high-speed system clock oscillationNote (See 5.6.1 (1) Example of setting procedure when oscillating the X1 clock and (2) Example of setting procedure when using the external main system clock.) Note The setting of <1> is not necessary when high-speed system clock is already operating. ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) or CHAPTER 27 ELECTRICAL SPECIFICATIONS ((A2) GRADE User's Manual U17555EJ3V0UD 129 www..com CHAPTER 5 CLOCK GENERATOR <2> Setting the high-speed system clock as the main system clock (MCM register) When XSEL and MCM0 are set to 1, the high-speed system clock is supplied as the main system clock and peripheral hardware clock. XSEL MCM0 Selection of Main System Clock and Clock Supplied to Peripheral Hardware Main System Clock (fXP) 1 1 High-speed system clock (fXH) Peripheral Hardware Clock (fPRS) High-speed system clock (fXH) Caution If the high-speed system clock is selected as the main system clock, a clock other than the high-speed system clock cannot be set as the peripheral hardware clock. <3> Setting the main system clock as the CPU clock and selecting the division ratio (PCC register) When CSS is cleared to 0, the main system clock is supplied to the CPU. To select the CPU clock division ratio, use PCC0, PCC1, and PCC2. CSS 0 PCC2 0 0 0 0 1 PCC1 0 0 1 1 0 Other than above PCC0 0 1 0 1 0 fXP fXP/2 (default) fXP/2 fXP/2 fXP/2 2 CPU Clock (fCPU) Selection 3 4 Setting prohibited (4) Example of setting procedure when stopping the high-speed system clock The high-speed system clock can be stopped in the following two ways. * Executing the STOP instruction and stopping the X1 oscillation (disabling clock input if the external clock is used) * Setting MSTOP to 1 and stopping the X1 oscillation (disabling clock input if the external clock is used) (a) To execute a STOP instruction <1> Setting to stop peripheral hardware Stop peripheral hardware that cannot be used in the STOP mode (for peripheral hardware that cannot be used in STOP mode, see CHAPTER 17 STANDBY FUNCTION). <2> Setting the X1 clock oscillation stabilization time after standby release When the CPU is operating on the X1 clock, set the value of the OSTS register before the STOP instruction is executed. <3> Executing the STOP instruction When the STOP instruction is executed, the system is placed in the STOP mode and X1 oscillation is stopped (the input of the external clock is disabled). 130 User's Manual U17555EJ3V0UD www..com CHAPTER 5 CLOCK GENERATOR (b) To stop X1 oscillation (disabling external clock input) by setting MSTOP to 1 <1> Confirming the CPU clock status (PCC and MCM registers) Confirm with CLS and MCS that the CPU is operating on a clock other than the high-speed system clock. When CLS = 0 and MCS = 1, the high-speed system clock is supplied to the CPU, so change the CPU clock to the subsystem clock or internal high-speed oscillation clock. CLS 0 0 1 MCS 0 1 x CPU Clock Status Internal high-speed oscillation clock High-speed system clock Subsystem clock <2> Stopping the high-speed system clock (MOC register) When MSTOP is set to 1, X1 oscillation is stopped (the input of the external clock is disabled). Caution Be sure to confirm that MCS = 0 or CLS = 1 when setting MSTOP to 1. In addition, stop peripheral hardware that is operating on the high-speed system clock. User's Manual U17555EJ3V0UD 131 www..com CHAPTER 5 CLOCK GENERATOR Note The setting of <1> is not necessary when the internal high-speed oscillation clock or highspeed system clock is already operating. <2> Selecting the clock supplied as the main system clock and peripheral hardware clock (MCM register) Set the main system clock and peripheral hardware clock using XSEL and MCM0. XSEL MCM0 Selection of Main System Clock and Clock Supplied to Peripheral Hardware Main System Clock (fXP) 0 0 1 0 1 0 Internal high-speed oscillation clock (fRH) Peripheral Hardware Clock (fPRS) Internal high-speed oscillation clock (fRH) High-speed system clock (fXH) <3> Selecting the CPU clock division ratio (PCC register) When CSS is cleared to 0, the main system clock is supplied to the CPU. To select the CPU clock division ratio, use PCC0, PCC1, and PCC2. CSS 0 PCC2 0 0 0 0 1 PCC1 0 0 1 1 0 Other than above PCC0 0 1 0 1 0 fXP fXP/2 (default) fXP/2 fXP/2 fXP/2 2 3 CPU Clock (fCPU) Selection 4 Setting prohibited (3) Example of setting procedure when stopping the internal high-speed oscillation clock The internal high-speed oscillation clock can be stopped in the following two ways. * Executing the STOP instruction to set the STOP mode * Setting RSTOP to 1 and stopping the internal high-speed oscillation clock (a) To execute a STOP instruction <1> Setting of peripheral hardware Stop peripheral hardware that cannot be used in the STOP mode (for peripheral hardware that cannot be used in STOP mode, see CHAPTER 17 STANDBY FUNCTION). <2> Setting the X1 clock oscillation stabilization time after standby release When the CPU is operating on the X1 clock, set the value of the OSTS register before the STOP instruction is executed. <3> Executing the STOP instruction When the STOP instruction is executed, the system is placed in the STOP mode and internal highspeed oscillation clock is stopped. 132 User's Manual U17555EJ3V0UD www..com CHAPTER 5 CLOCK GENERATOR (b) To stop internal high-speed oscillation clock by setting RSTOP to 1 <1> Confirming the CPU clock status (PCC and MCM registers) Confirm with CLS and MCS that the CPU is operating on a clock other than the internal high-speed oscillation clock. When CLS = 0 and MCS = 0, the internal high-speed oscillation clock is supplied to the CPU, so change the CPU clock to the high-speed system clock or subsystem clock. CLS 0 0 1 MCS 0 1 x CPU Clock Status Internal high-speed oscillation clock High-speed system clock Subsystem clock <2> Stopping the internal high-speed oscillation clock (RCM register) When RSTOP is set to 1, internal high-speed oscillation clock is stopped. Caution Be sure to confirm that MCS = 1 or CLS = 1 when setting RSTOP to 1. In addition, stop peripheral hardware that is operating on the internal high-speed oscillation clock. * External subsystem clock: External clock is input to the EXCLKS pin. When the subsystem clock is not used, the XT1/P123 and XT2/EXCLKS/P124 pins can be used as I/O port pins. Caution The XT1/P123 and XT2/EXCLKS/P124 pins are in the I/O port mode after a reset release. The following describes examples of setting procedures for the following cases. (1) When oscillating XT1 clock (2) When using external subsystem clock (3) When using subsystem clock as CPU clock (4) When stopping subsystem clock (1) Example of setting procedure when oscillating the XT1 clock <1> Setting XT1 and XT2 pins and selecting operation mode (PCC and OSCCTL registers) When XTSTART, EXCLKS, and OSCSELS are set as any of the following, the mode is switched from port mode to XT1 oscillation mode. XTSTART EXCLKS OSCSELS Operation Mode of Subsystem Clock Pin 0 1 0 x 1 x XT1 oscillation mode P123/XT1 Pin P124/XT2/ EXCLKS Pin Crystal/ceramic resonator connection Remark x: don't care <2> Waiting for the stabilization of the subsystem clock oscillation Wait for the oscillation stabilization time of the subsystem clock by software, using a timer function. Caution Do not change the value of XTSTART, EXCLKS, and OSCSELS while the subsystem clock is operating. User's Manual U17555EJ3V0UD 133 www..com CHAPTER 5 CLOCK GENERATOR (2) Example of setting procedure when using the external subsystem clock <1> Setting XT1 and XT2 pins, selecting XT1 clock/external clock and controlling oscillation (PCC and OSCCTL registers) When XTSTART is cleared to 0 and EXCLKS and OSCSELS are set to 1, the mode is switched from port mode to external clock input mode. In this case, input the external clock to the EXCLKS/XT2/P124 pins. XTSTART 0 EXCLKS 1 OSCSELS 1 Operation Mode of Subsystem Clock Pin External clock input mode P123/XT1 Pin I/O port P124/XT2/ EXCLKS Pin External clock input Caution Do not change the value of XTSTART, EXCLKS, and OSCSELS while the subsystem clock is operating. (3) Example of setting procedure when using the subsystem clock as the CPU clock <1> Setting subsystem clock oscillationNote (See 5.6.3 (1) Example of setting procedure when oscillating the XT1 clock and (2) Example of setting procedure when using the external subsystem clock.) Note The setting of <1> is not necessary when while the subsystem clock is operating. <2> Switching the CPU clock (PCC register) When CSS is set to 1, the subsystem clock is supplied to the CPU. CSS 1 PCC2 0 0 0 0 1 PCC1 0 0 1 1 0 Other than above PCC0 0 1 0 1 0 Setting prohibited fSUB/2 CPU Clock (fCPU) Selection (4) Example of setting procedure when stopping the subsystem clock <1> Confirming the CPU clock status (PCC and MCM registers) Confirm with CLS and MCS that the CPU is operating on a clock other than the subsystem clock. When CLS = 1, the subsystem clock is supplied to the CPU, so change the CPU clock to the internal high-speed oscillation clock or high-speed system clock. CLS 0 0 1 MCS 0 1 x CPU Clock Status Internal high-speed oscillation clock High-speed system clock Subsystem clock <2> Stopping the subsystem clock (OSCCTL register) When OSCSELS is cleared to 0, XT1 oscillation is stopped (the input of the external clock is disabled). Caution1. Be sure to confirm that CLS = 0 when clearing OSCSELS to 0. In addition, stop the watch timer if it is operating on the subsystem clock. 2. The subsystem clock oscillation cannot be stopped using the STOP instruction. 134 User's Manual U17555EJ3V0UD www..com CHAPTER 5 CLOCK GENERATOR 5.6.4 Controlling internal low-speed oscillation clock The internal low-speed oscillation clock is a clock for the watchdog timer. It cannot be used as the CPU clock. With this clock, only the following peripheral hardware can operate. * Watchdog timer * 8-bit timer H1 (if fRL is selected as the count clock) In addition, the following operation modes can be selected by the option byte. * Internal low-speed oscillation clock oscillation cannot be stopped * Internal low-speed oscillation clock oscillation can be stopped by software After a reset release, the internal low-speed oscillation clock automatically oscillates. (1) To stop the internal low-speed oscillation clock (example of setting method) <1> Setting LSRSTOP to 1 (RCM register) If LSRSTOP is set to 1, the internal low-speed oscillator oscillation is stopped. (2) To oscillate the internal low-speed oscillation clock (example of setting method) <1> Clearing LSRSTOP to 0 (RCM register) If LSRSTOP is cleared to 0, the internal low-speed oscillation clock is oscillated. Caution If "internal low-speed oscillation clock oscillation cannot be stopped" is selected by the option byte, oscillation of the internal low-speed oscillation clock cannot be controlled. 5.6.5 Clocks supplied to CPU and peripheral hardware The following table shows the relation among the clocks supplied to the CPU and peripheral hardware, and setting of registers. Table 5-3. Clocks Supplied to CPU and Peripheral Hardware, and Register Setting XSEL CSS MCM0 EXCLK Supplied Clock Clock Supplied to CPU Clock Supplied to Peripheral Hardware 0 0 0 1 x x x x Internal high-speed oscillation clock Subsystem clock Internal high-speed oscillation clock 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Internal high-speed oscillation clock X1 clock External main system clock Subsystem clock X1 clock External main system clock X1 clock External main system clock X1 clock External main system clock Remarks 1. 2. 3. 4. XSEL: CSS: Bit 2 of the main clock mode register (MCM) Bit 4 of the processor clock control register (PCC) MCM0: Bit 0 of MCM EXCLK: Bit 7 of the clock operation mode select register (OSCCTL) User's Manual U17555EJ3V0UD 135 www..com CHAPTER 5 CLOCK GENERATOR 5.6.6 CPU clock status transition diagram Figure 5-14 shows the CPU clock status transition diagram of this product. Figure 5-14. CPU Clock Status Transition Diagram Internal low-speed oscillation: Woken up Internal high-speed oscillation: Woken up X1 oscillation/EXCLK input: Stops (I/O port mode) XT1 oscillation/EXCLKS input: Stops (I/O port mode) Power ON VDD < 1.59 V (TYP.) (A) Reset release VDD 1.59 V (TYP.) Internal low-speed oscillation: Operating Internal high-speed oscillation: Operating X1 oscillation/EXCLK input: Stops (I/O port mode) XT1 oscillation/EXCLKS input: Stops (I/O port mode) Internal low-speed oscillation: Operable Internal high-speed oscillation: Selectable by CPU X1 oscillation/EXCLK input: Selectable by CPU XT1 oscillation/EXCLKS input: Operating (D) Internal low-speed oscillation: Operable Internal high-speed oscillation: Operating X1 oscillation/EXCLK input: Selectable by CPU XT1 oscillation/EXCLKS input: Selectable by CPU (B) VDD 1.8 V (MIN.) CPU: Operating with internal highspeed oscillation (H) CPU: Internal highspeed oscillation STOP Internal low-speed oscillation: Operable Internal high-speed oscillation: Stops X1 oscillation/EXCLK input: Stops XT1 oscillation/EXCLKS input: Operable CPU: Operating with XT1 oscillation or EXCLKS input (E) (C) CPU: Operating with X1 oscillation or EXCLK input CPU: Internal highspeed oscillation HALT (G) CPU: XT1 oscillation/EXCLKS input HALT Internal low-speed oscillation: Operable Internal high-speed oscillation: Operable X1 oscillation/EXCLK input: Operable XT1 oscillation/EXCLKS input: Operating Internal low-speed oscillation: Operable Internal high-speed oscillation: Operating X1 oscillation/EXCLK input: Operable XT1 oscillation/EXCLKS input: Operable Internal low-speed oscillation: Operable Internal high-speed oscillation: Selectable by CPU X1 oscillation/EXCLK input: Operating XT1 oscillation/EXCLKS input: Selectable by CPU (I) (F) CPU: X1 oscillation/EXCLK input HALT Internal low-speed oscillation: Operable Internal high-speed oscillation: Operable X1 oscillation/EXCLK input: Operating XT1 oscillation/EXCLKS input: Operable CPU: X1 oscillation/EXCLK input STOP Internal low-speed oscillation: Operable Internal high-speed oscillation: Stops X1 oscillation/EXCLK input: Stops XT1 oscillation: Operable Remark In the 2.7 V/1.59 V POC mode (option byte: LVISTART = 1), the CPU clock status changes to (A) in the above figure when the supply voltage exceeds 2.7 V (TYP.), and to (B) after reset processing (11 to 45 s). 136 User's Manual U17555EJ3V0UD www..com CHAPTER 5 CLOCK GENERATOR Table 5-4 shows transition of the CPU clock and examples of setting the SFR registers. Table 5-4. CPU Clock Transition and SFR Register Setting Examples (1/4) (1) CPU operating with high-speed system clock (C) after reset release (A) (The CPU operates with the internal high-speed oscillation clock immediately after a reset release (B).) (Setting sequence of SFR registers) Setting Flag of SFR Register Status Transition (A) (B) (C) (X1 clock: less than 10 MHz) (A) (B) (C) (external main clock: less than 10 MHz) (A) (B) (C) (X1 clock: 10 MHz or more) (A) (B) (C) (external main clock: 10 MHz or more) 1 0 1 0 0 0 1 0 AMPH EXCLK OSCSEL MSTOP OSTC Register Must be checked 0 1 1 0 Must not be checked XSEL MCM0 1 1 1 1 Must be checked 1 1 1 1 1 0 Must not be checked 1 1 (2) CPU operating with internal high-speed oscillation clock (B) after reset release (A) Status Transition (A) (B) SFR Register Setting SFR registers do not have to be set (default status after reset release). (3) CPU operating with subsystem clock (D) after reset release (A) (The CPU operates with the internal high-speed oscillation clock immediately after a reset release (B).) (Setting sequence of SFR registers) Setting Flag of SFR Register Status Transition (A) (B) (D) (XT1 clock) (A) (B) (D) (external subsystem clock) 0 1 1 1 EXCLKS OSCSELS Waiting for Oscillation Stabilization Necessary Unnecessary 1 1 CSS Remarks 1. 2. (A) to (I) in Table 5-4 correspond to (A) to (I) in Figure 5-14. EXCLK, OSCSEL, EXCLKS, OSCSELS, AMPH: Bits 7 to 4 and 0 of the clock operation mode select register (OSCCTL) MSTOP: CSS: Bit 7 of the main OSC control register (MOC) Bit 4 of the processor clock control register (PCC) XSEL, MCM0: Bits 2 and 0 of the main clock mode register (MCM) User's Manual U17555EJ3V0UD 137 www..com CHAPTER 5 CLOCK GENERATOR Table 5-4. CPU Clock Transition and SFR Register Setting Examples (2/4) (4) CPU clock changing from internal high-speed oscillation clock (B) to high-speed system clock (C) (Setting sequence of SFR registers) Setting Flag of SFR Register Status Transition (B) (C) (X1 clock: less than 10 MHz) (B) (C) (external main clock: less than 10 MHz) (B) (C) (X1 clock: 10 MHz or more) (B) (C) (external main clock: 10 MHz or more) 0 0 1 0 AMPH EXCLK OSCSEL MSTOP OSTC Register Must be checked 0 1 1 0 Must not be checked XSEL MCM0 1 1 1 1 1 0 1 0 Must be checked 1 1 1 1 1 0 Must not be checked 1 1 Unnecessary if these registers are already set Unnecessary if the CPU is operating with the high-speed system clock Unnecessary if this register is already set (5) CPU clock changing from internal high-speed oscillation clock (B) to subsystem clock (D) (Setting sequence of SFR registers) Setting Flag of SFR Register Status Transition (B) (D) (XT1 clock) (B) (D) (external subsystem clock) 0 1 1 1 EXCLKS OSCSELS Waiting for Oscillation Stabilization Necessary Unnecessary 1 1 CSS Unnecessary if the CPU is operating with the subsystem clock Remarks 1. 2. (A) to (I) in Table 5-4 correspond to (A) to (I) in Figure 5-14. EXCLK, OSCSEL, EXCLKS, OSCSELS, AMPH: Bits 7 to 4 and 0 of the clock operation mode select register (OSCCTL) MSTOP: CSS: Bit 7 of the main OSC control register (MOC) Bit 4 of the processor clock control register (PCC) XSEL, MCM0: Bits 2 and 0 of the main clock mode register (MCM) 138 User's Manual U17555EJ3V0UD www..com CHAPTER 5 CLOCK GENERATOR Table 5-4. CPU Clock Transition and SFR Register Setting Examples (3/4) (6) CPU clock changing from high-speed system clock (C) to internal high-speed oscillation clock (B) (Setting sequence of SFR registers) Setting Flag of SFR Register Status Transition (C) (B) 0 Confirm this flag is 1. 0 RSTOP RSTS MCM0 Unnecessary if the CPU is operating with the internal high-speed oscillation clock (7) CPU clock changing from high-speed system clock (C) to subsystem clock (D) (Setting sequence of SFR registers) Setting Flag of SFR Register Status Transition (C) (D) (XT1 clock) (C) (D) (external subsystem clock) 0 1 1 1 EXCLKS OSCSELS Waiting for Oscillation Stabilization Necessary Unnecessary 1 1 CSS Unnecessary if the CPU is operating with the subsystem clock (8) CPU clock changing from subsystem clock (D) to high-speed system clock (C) (Setting sequence of SFR registers) Setting Flag of SFR Register Status Transition (D) (C) (X1 clock: less than 10 MHz) (D) (C) (external main clock: less than 10 MHz) (D) (C) (X1 clock: 10 MHz or more) (D) (C) (external main clock: 10 MHz or more) 1 0 1 0 0 0 1 0 AMPH EXCLK OSCSEL MSTOP OSTC Register Must be checked 0 1 1 0 Must not be checked XSEL MCM0 CSS 1 1 0 1 1 0 Must be checked 1 1 0 1 1 1 0 Must not be checked 1 1 0 Unnecessary if these registers are already set Unnecessary if the CPU is operating with the high-speed system clock Unnecessary if this register is already set Remarks 1. 2. (A) to (I) in Table 5-4 correspond to (A) to (I) in Figure 5-14. EXCLK, OSCSEL, EXCLKS, OSCSELS, AMPH: Bits 7 to 4 and 0 of the clock operation mode select register (OSCCTL) MSTOP: XSEL, MCM0: CSS: Bit 7 of the main OSC control register (MOC) Bits 2 and 0 of the main clock mode register (MCM) Bit 4 of the processor clock control register (PCC) RSTS, RSTOP: Bits 7 and 0 of the internal oscillator mode register (RCM) User's Manual U17555EJ3V0UD 139 www..com CHAPTER 5 CLOCK GENERATOR Table 5-4. CPU Clock Transition and SFR Register Setting Examples (4/4) (9) CPU clock changing from subsystem clock (D) to internal high-speed oscillation clock (B) (Setting sequence of SFR registers) Setting Flag of SFR Register Status Transition (D) (B) 0 Confirm this flag is 1. Unnecessary if the CPU is operating with the internal high-speed oscillation clock Unnecessary if XSEL is 0 0 0 RSTOP RSTS MCM0 CSS (10) * HALT mode (E) set while CPU is operating with internal high-speed oscillation clock (B) * HALT mode (F) set while CPU is operating with high-speed system clock (C) * HALT mode (G) set while CPU is operating with subsystem clock (D) Status Transition (B) (E) (C) (F) (D) (G) Executing HALT instruction Setting (11) * STOP mode (H) set while CPU is operating with internal high-speed oscillation clock (B) * STOP mode (I) set while CPU is operating with high-speed system clock (C) (Setting sequence) Status Transition (B) (H) (C) (I) Stopping peripheral functions that cannot operate in STOP mode Setting Executing STOP instruction Remarks 1. 2. (A) to (I) in Table 5-4 correspond to (A) to (I) in Figure 5-14. MCM0: CSS: Bit 0 of the main clock mode register (MCM) Bit 4 of the processor clock control register (PCC) RSTS, RSTOP: Bits 7 and 0 of the internal oscillator mode register (RCM) 140 User's Manual U17555EJ3V0UD www..com CHAPTER 5 CLOCK GENERATOR 5.6.7 Condition before changing CPU clock and processing after changing CPU clock Condition before changing the CPU clock and processing after changing the CPU clock are shown below. Table 5-5. Changing CPU Clock CPU Clock Before Change Internal highspeed oscillation After Change X1 clock Stabilization of X1 oscillation * MSTOP = 0, OSCSEL = 1, EXCLK = 0 * After elapse of oscillation stabilization time External main system clock Enabling input of external clock from EXCLK pin * MSTOP = 0, OSCSEL = 1, EXCLK = 1 * Internal high-speed oscillator can be stopped (RSTOP = 1). * Clock supply to CPU is stopped for 4.06 to 16.12 s after AMPH has been set to 1. * Internal high-speed oscillator can be stopped (RSTOP = 1). * Clock supply to CPU is stopped for the duration of 160 external clocks from the EXCLK pin after AMPH has been set to 1. X1 clock External main system clock Internal highspeed oscillation clock X1 clock External main system clock Internal highspeed oscillation clock X1 clock External main system clock XT1 clock, external subsystem clock Internal highspeed oscillation clock Oscillation of internal high-speed oscillator and selection of internal high-speed oscillation clock as main system clock * RSTOP = 0, MCS = 0 X1 clock Stabilization of X1 oscillation and selection of high-speed system clock as main system clock * XT1 oscillation can be stopped or external subsystem clock input can be disabled (OSCSELS = 0). * Clock supply to CPU is stopped for 4.06 to 16.12 s after AMPH has been set to 1. * XT1 oscillation can be stopped or external subsystem clock input can be disabled (OSCSELS = 0). * Clock supply to CPU is stopped for the duration of 160 external clocks from the EXCLK pin after AMPH has been set to 1. External subsystem clock Enabling input of external clock from EXCLKS pin * XTSTART = 0, EXCLKS = 1, OSCSELS = 1 Internal highspeed oscillation clock XT1 clock Stabilization of XT1 oscillation * XTSTART = 0, EXCLKS = 0, OSCSELS = 1, or XTSTART = 1 * After elapse of oscillation stabilization time Oscillation of internal high-speed oscillator * RSTOP = 0 X1 oscillation can be stopped (MSTOP = 1). External main system clock input can be disabled (MSTOP = 1). Operating current can be reduced by stopping internal high-speed oscillator (RSTOP = 1). X1 oscillation can be stopped (MSTOP = 1). External main system clock input can be disabled (MSTOP = 1). Operating current can be reduced by stopping internal high-speed oscillator (RSTOP = 1). X1 oscillation can be stopped (MSTOP = 1). External main system clock input can be disabled (MSTOP = 1). XT1 oscillation can be stopped or external subsystem clock input can be disabled (OSCSELS = 0). Condition Before Change Processing After Change clock * MSTOP = 0, OSCSEL = 1, EXCLK = 0 * After elapse of oscillation stabilization time * MCS = 1 External main system clock Enabling input of external clock from EXCLK pin and selection of high-speed system clock as main system clock * MSTOP = 0, OSCSEL = 1, EXCLK = 1 * MCS = 1 User's Manual U17555EJ3V0UD 141 www..com CHAPTER 5 CLOCK GENERATOR Set Value Before Switchover CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 Set Value After Switchover 0 0 0 0 0 0 1 1 x 0 0 1 1 0 x 0 1 0 1 0 x 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 1 x x x 16 clocks 8 clocks 4 clocks 2 clocks 1 clock 2 clocks 4 clocks 2 clocks 1 clock 2 clocks 16 clocks 8 clocks 16 clocks 8 clocks 4 clocks 16 clocks 8 clocks 4 clocks 2 clocks 2fXP/fSUB clocks fXP/fSUB clocks fXP/2fSUB clocks fXP/4fSUB clocks fXP/8fSUB clocks 2 clocks 1 clock 2 clocks 1 clock 2 clocks 2 clocks Caution Selection of the main system clock cycle division factor (PCC0 to PCC2) and switchover from the main system clock to the subsystem clock (changing CSS from 0 to 1) should not be set simultaneously. Simultaneous setting is possible, however, for selection of the main system clock cycle division factor (PCC0 to PCC2) and switchover from the subsystem clock to the main system clock (changing CSS from 1 to 0). Remarks 1. The number of clocks listed in Table 5-6 is the number of CPU clocks before switchover. 2. When switching the CPU clock from the main system clock to the subsystem clock, calculate the number of clocks by rounding up to the next clock and discarding the decimal portion, as shown below. Example When switching CPU clock from fXP/2 to fSUB/2 (@ oscillation with fXP = 10 MHz, fSUB = 32.768 kHz) fXP/fSUB = 10000/32.768 305.1 306 clocks By setting bit 0 (MCM0) of the main clock mode register (MCM), the main system clock can be switched (between the internal high-speed oscillation clock and the high-speed system clock). The actual switchover operation is not performed immediately after rewriting to MCM0; operation continues on the pre-switchover clock for several clocks (see Table 5-7). Whether the CPU is operating on the internal high-speed oscillation clock or the high-speed system clock can be ascertained using bit 1 (MCS) of MCM. 142 User's Manual U17555EJ3V0UD www..com CHAPTER 5 CLOCK GENERATOR Table 5-7. Maximum Time Required for Main System Clock Switchover Set Value Before Switchover MCM0 0 0 1 1 + 2fXH/fRH clock Set Value After Switchover MCM0 1 1 + 2fRH/fXH clock Caution When switching the internal high-speed oscillation clock to the high-speed system clock, bit 2 (XSEL) of MCM must be set to 1 in advance. The value of XSEL can be changed only once after a reset release. Remarks 1. The number of clocks listed in Table 5-7 is the number of main system clocks before switchover. 2. Calculate the number of clocks in Table 5-7 by removing the decimal portion. Example When switching the main system clock from the internal high-speed oscillation clock to the high-speed system clock (@ oscillation with fRH = 8 MHz, fXH = 10 MHz) 1 + 2fRH/fXH = 1 + 2 x 8/10 = 1 + 2 x 0.8 = 1 + 1.6 = 2.6 2 clocks Clock Conditions Before Clock Oscillation Is Stopped (External Clock Input Disabled) Internal high-speed oscillation clock MCS = 1 or CLS = 1 (The CPU is operating on a clock other than the internal high-speed oscillation clock) X1 clock External main system clock XT1 clock External subsystem clock MCS = 0 or CLS = 1 (The CPU is operating on a clock other than the high-speed system clock) CLS = 0 (The CPU is operating on a clock other than the subsystem clock) OSCSELS = 0 MSTOP = 1 Flag Settings of SFR Register RSTOP = 1 User's Manual U17555EJ3V0UD 143 www..com CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 The 78K0/FC2 incorporates 16-bit timer/event counters 00 and 01. Since the composition of a timer I/O pin changes with products, the 16-bit timer/event counter 01 (TM01) has the difference of function in a 16-bir timer/event counter00 (TM00). The difference in the function by the product is shown below. Product Pin TI001 TI011 TO01 PD78F0881, 78F0882 and 78F0883 - - - PD78F0884, 78F0885 and 78F0886 - Provided Provided Be careful to the following restrictions for function of TM01 for PD78F0881, 78F0882 and 78F0883. * Selecting TI001 and TI011 for count clock is prohibited. When Using TI001 for baud rate error calculation, it is not applicable. * Timer output is prohibited. Be careful to the following restrictions for function of TM01 for PD78F0884, 78F0885 and 78F0886. * Selecting TI001 for count clock is prohibited. applicable. When Using TI001 for baud rate error calculation, it is not 144 User's Manual U17555EJ3V0UD www..com CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 6.1 Functions of 16-Bit Timer/Event Counters 00 and 01 16-bit timer/event counters 00 and 01 have the following functions. * Interval timer * PPG output * Pulse width measurement * External event counter * Square-wave output * One-shot pulse output (1) Interval timer 16-bit timer/event counters 00 and 01 generate an interrupt request at the preset time interval. (2) PPG output 16-bit timer/event counters 00 and 01 can output a rectangular wave whose frequency and output pulse width can be set freely. (3) Pulse width measurement 16-bit timer/event counters 00 and 01 can measure the pulse width of an externally input signal. (4) External event counter 16-bit timer/event counters 00 and 01 can measure the number of pulses of an externally input signal. (5) Square-wave output 16-bit timer/event counters 00 and 01 can output a square wave with any selected frequency. (6) One-shot pulse output 16-bit timer event counters 00 and 01 can output a one-shot pulse whose output pulse width can be set freely. User's Manual U17555EJ3V0UD 145 www..com CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 6.2 Configuration of 16-Bit Timer/Event Counters 00 and 01 16-bit timer/event counters 00 and 01 include the following hardware. Table 6-1. Configuration of 16-Bit Timer/Event Counters 00 and 01 Item Timer counter Register Timer input Timer output Control registers 16 bits (TM0n) 16-bit timer capture/compare register: 16 bits (CR00n, CR01n) TI000, TI01n TO0n, output controller 16-bit timer mode control register 0n (TMC0n) 16-bit timer capture/compare control register 0n (CRC0n) 16-bit timer output control register 0n (TOC0n) Prescaler mode register 0n (PRM0n) Port mode register 0 (PM0) Port register 0 (P0) Configuration Remarks 1. There are no TI001, TI011 and TO01 in PD78F0881, 78F0882 and 78F0883. 2. There is no TI001 in PD78F0884, 78F0885 and 78F0886. 3. n = 0, 1 Figures 6-1, 6-2 and 6-3 show the block diagrams. Figure 6-1. Block Diagram of 16-Bit Timer/Event Counter 00 Internal bus Capture/compare control register 00 (CRC00) CRC002CRC001 CRC000 Selector INTTM000 Selector TI010/TO00/P01 Noise eliminator 16-bit timer capture/compare register 000 (CR000) Match Selector fPRS fPRS/22 fPRS/28 16-bit timer counter 00 (TM00) Match Clear Output controller Output latch (P01) PM01 TO00/TI010/ P01 fPRS Noise eliminator 2 Noise eliminator 16-bit timer capture/compare register 010 (CR010) Selector TI000/P00 INTTM010 CRC002 PRM001 PRM000 Prescaler mode register 00 (PRM00) TMC003 TMC002 TMC001 OVF00 OSPT00 OSPE00 TOC004 LVS00 LVR00 TOC001 TOE00 16-bit timer output 16-bit timer mode control register 00 control register 00 (TOC00) (TMC00) Internal bus 146 User's Manual U17555EJ3V0UD www..com CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 6-2. Block Diagram of 16-Bit Timer/Event Counter 01 (PD78F0881, 78F0882, 78F0883) Capture/compare control register 01 (CRC01) CRC012CRC011 CRC010 Selector Internal bus INTTM001 Selector Noise eliminator 16-bit timer capture/compare register 001 (CR001) Match Selector fPRS fPRS/24 fPRS/26 16-bit timer counter 01 (TM01) Match Clear Output controller fPRS Noise eliminator 2 Noise eliminator 16-bit timer capture/compare register 011 (CR011) Selector INTTM011 CRC012 PRM011 PRM010 Prescaler mode register 01 (PRM01) TMC013 TMC012 TMC011 OVF01 OSPT01 OSPE01 TOC014 LVS01 LVR01 TOC011 TOE01 16-bit timer output 16-bit timer mode control register 01 control register 01 (TOC01) (TMC01) Internal bus Figure 6-3. Block Diagram of 16-Bit Timer/Event Counter 01 (PD78F0884, 78F0885, 78F0886) Capture/compare control register 01 (CRC01) CRC012CRC011 CRC010 Selector Internal bus INTTM001 Selector TI011/TO01/P06 Noise eliminator 16-bit timer capture/compare register 001 (CR001) Match Selector fPRS fPRS/24 fPRS/26 16-bit timer counter 01 (TM01) Match Clear Output controller Output latch (P06) PM06 TO01/TI011/ P06 fPRS Noise eliminator 2 Noise eliminator 16-bit timer capture/compare register 011 (CR011) Selector INTTM011 CRC012 PRM011 PRM010 Prescaler mode register 01 (PRM01) TMC013 TMC012 TMC011 OVF01 OSPT01 OSPE01 TOC014 LVS01 LVR01 TOC011 TOE01 16-bit timer output 16-bit timer mode control register 01 control register 01 (TOC01) (TMC01) Internal bus User's Manual U17555EJ3V0UD 147 www..com CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (1) 16-bit timer counter 0n (TM0n) TM0n is a 16-bit read-only register that counts count pulses. The counter is incremented in synchronization with the rising edge of the input clock. Address: FF10H, FF11H (TM00), FFB0H, FFB1H (TM01) Symbol FF11H (TM00) FFB1H (TM01) After reset: 0000H R FF10H (TM00) FFB0H (TM01) TM0n (n = 0, 1) The count value is reset to 0000H in the following cases. <1> At reset signal generation <2> If TMC0n3 and TMC0n2 are cleared <3> If the valid edge of the TI000 pin is input in the mode in which clear & start occurs when inputting the valid edge of the TI000 pin <4> If TM0n and CR00n match in the mode in which clear & start occurs on a match of TM0n and CR00n 148 User's Manual U17555EJ3V0UD www..com CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (2) 16-bit timer capture/compare register 00n (CR00n) CR00n is a 16-bit register that has the functions of both a capture register and a compare register. Whether it is used as a capture register or as a compare register is set by bit 0 (CRC0n0) of capture/compare control register 0n (CRC0n). CR00n can be set by a 16-bit memory manipulation instruction. Reset signal generation clears this register to 0000H. Figure 6-5. Format of 16-Bit Timer Capture/Compare Register 00n (CR00n) Address: FF12H, FF13H (CR000), FFB2H, FFB3H (CR001) Symbol FF13H (CR000) FFB2H (CR001) After reset: 0000H R/W FF12H (CR000) FFB3H (CR001) CR00n (n = 0, 1) * When CR00n is used as a compare register The value set in CR00n is constantly compared with 16-bit timer counter 0n (TM0n) count value, and an interrupt request (INTTM00n) is generated if they match. The set value is held until CR00n is rewritten. * When CR00n is used as a capture register It is possible to select the valid edge of the TI000 pin or the TI01n pin as the capture trigger. The TI000 or TI01n pin valid edge is set using prescaler mode register 0n (PRM0n) (see Table 6-2). User's Manual U17555EJ3V0UD 149 www..com CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Table 6-2. CR00n Capture Trigger and Valid Edges of TI000 and TI01n Pins (1) TI000 pin valid edge selected as capture trigger (CRC001 = 1, CRC000 = 1) CR000 Capture Trigger TI000 Pin Valid Edge ES001 Falling edge Rising edge No capture operation Rising edge Falling edge Both rising and falling edges 0 0 1 ES000 1 0 1 (2) TI01n pin valid edge selected as capture trigger (CRC0n1 = 0, CRC0n0 = 1) CR00n Capture Trigger TI01n Pin Valid Edge ES1n1 Falling edge Rising edge Both rising and falling edges Falling edge Rising edge Both rising and falling edges 0 0 1 ES1n0 0 1 1 Cautions 1. Set a value other than 0000H in CR00n in the mode in which clear & start occurs on a match of TM0n and CR00n. 2. If CR00n is cleared to 0000H in the free-running mode and an interrupt request (INTTM00n) is generated when the value of CR00n changes from 0000H to 0001H following TM0n overflow (FFFFH). In addition, INTTM00n is generated after a match between TM0n and CR00n, after detecting the valid edge of the TI01n pin, and the timer is cleared by a one-shot trigger. 3. When P01 or P06 is used as the valid edge input of the TI01n pin, it cannot be used as the timer output (TO0n). Moreover, when P01 or P06 is used as TO0n, it cannot be used as the valid edge input of the TI01n pin. 4. When CR00n is used as a capture register, read data is undefined if the register read time and capture trigger input conflict (the capture data itself is the correct value). If count stop input and capture trigger input conflict, the captured data is undefined. 5. Do not rewrite CR00n during TM0n operation. Remarks 1. Setting ES001, ES000 = 1, 0 and ES1n1, ES1n0 = 1, 0 is prohibited. 2. ES001, ES000: ES1n1, ES1n0: 3. n = 0, 1 Bits 5 and 4 of prescaler mode register 00 (PRM00) Bits 7 and 6 of prescaler mode register 0n (PRM0n) CRC0n1, CRC0n0: Bits 1 and 0 of capture/compare control register 0n (CRC0n) 150 User's Manual U17555EJ3V0UD www..com CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (3) 16-bit timer capture/compare register 01n (CR01n) CR01n is a 16-bit register that has the functions of both a capture register and a compare register. Whether it is used as a capture register or a compare register is set by bit 2 (CRC002) of capture/compare control register 00 (CRC00). CR01n can be set by a 16-bit memory manipulation instruction. Reset signal generation clears this register to 0000H. Figure 6-6. Format of 16-Bit Timer Capture/Compare Register 01n (CR01n) Address: FF14H, FF15H (CR010), FFB4H, FFB5H (CR011) Symbol FF15H (CR010) FFB5H (CR011) After reset: 0000H R/W FF14H (CR010) FFB4H (CR011) CR01n (n = 0, 1) * When CR01n is used as a compare register The value set in the CR01n is constantly compared with 16-bit timer counter 0n (TM0n) count value, and an interrupt request (INTTM01n) is generated if they match. The set value is held until CR01n is rewritten. * When CR010 is used as a capture register It is possible to select the valid edge of the TI000 pin as the capture trigger. The TI000 pin valid edge is set by prescaler mode register 00 (PRM00) (see Table 6-3). Table 6-3. CR01n Capture Trigger and Valid Edge of TI000 Pin (CRC002 = 1) CR010 Capture Trigger TI000 Pin Valid Edge ES001 Falling edge Rising edge Both rising and falling edges Falling edge Rising edge Both rising and falling edges 0 0 1 ES000 0 1 1 Cautions 1. If the CR01n register is cleared to 0000H, an interrupt request (INTTM01n) is generated when the value of CR01n changes from 0000H to 0001H following TM0n overflow (FFFFH). In addition, INTTM01n is generated after a match between TM0n and CR01n, after detecting the valid edge of the TI000 pin, and the timer is cleared by a one-shot trigger. 2. When CR01n is used as a capture register, read data is undefined if the register read time and capture trigger input conflict (the capture data itself is the correct value). If count stop input and capture trigger input conflict, the captured data is undefined. 3. CR01n can be rewritten during TM0n operation. For details, see Caution 2 in Figure 6-22 PPG Output Operation Timing. Remarks 1. Setting ES001, ES000 = 1, 0 is prohibited. 2. ES001, ES000: Bits 5 and 4 of prescaler mode register 00 (PRM00) CRC002: 3. n = 0, 1 Bit 2 of capture/compare control register 00 (CRC00) User's Manual U17555EJ3V0UD 151 www..com CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Operation Operation as interval timer Operation as square-wave output Operation as external event counter Operation in the clear & start mode entered by TI000 pin valid edge input Operation as free-running timer Operation as PPG output Operation as one-shot pulse output M < N FFFFH 0000H Note CR00n Register Setting Range 0000H < N FFFFH 0000H CR01n Register Setting Range Note M FFFFH Normally, this setting is not used. Mask the match interrupt signal (INTTM01n). 0000H Note N FFFFH 0000H Note M FFFFH 0000H Note M 0000H Note Note When 0000H is set, a match interrupt immediately after the timer operation does not occur and timer output is not changed, and the first match timing is as follows. A match interrupt occurs at the timing when the timer counter (TM0n register) is changed from 0000H to 0001H. * When the timer counter is cleared due to overflow * When the timer counter is cleared due to TI000 pin valid edge (when clear & start mode is entered by TI000 pin valid edge input) * When the timer counter is cleared due to compare match (when clear & start mode is entered by match between TM0n and CR00n (CR00n = other than 0000H, CR01n = 0000H)) Timer counter clear TM0n register Compare register set value (0000H) Operation Timer operation enable bit disabled (00) (TMC0n3, TMC0n2) Operation enabled (other than 00) Interrupt request signal Interrupt signal is not generated Interrupt signal is generated Remarks 1. N: CR00n register set value, M: CR01n register set value 2. For details of TMC0n3 and TMC0n2, see 6.3 (1) 16-bit timer mode control register 0n (TMC0n). 3. n = 0, 1 152 User's Manual U17555EJ3V0UD www..com CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Table 6-4. Capture Operation of CR00n and CR01n External Input Signal Capture Operation Capture operation of CR00n CRC001 = 1 TI000 pin input (reverse phase) Set values of ES001 and ES000 Position of edge to be captured 01: Rising CRC0n1 bit = 0 TI01n pin input Set values of ES1n1 and ES1n0 Position of edge to be captured 01: Rising TI000 Pin Input TI01n Pin Input 00: Falling 00: Falling 11: Both edges (cannot be captured) Interrupt signal INTTM000 signal is not generated even if value is captured. Capture operation of CR010 TI000 pin input Note 11: Both edges Interrupt signal INTTM00n signal is generated each time value is captured. Set values of ES001 and ES000 Position of edge to be captured 01: Rising 00: Falling 11: Both edges Interrupt signal INTTM010 signal is generated each time value is captured. Note The capture operation of CR010 is not affected by the setting of the CRC001 bit. Caution To capture the count value of the TM00 register to the CR000 register by using the phase reverse to that input to the TI000 pin, the interrupt request signal (INTTM000) is not generated after the value has been captured. If the valid edge is detected on the TI010 pin during this operation, the capture operation is not performed but the INTTM000 signal is generated as an external interrupt signal. To not use the external interrupt, mask the INTTM000 signal. Remarks 1. CRC0n1: See 6.3 (2) Capture/compare control register 0n (CRC0n). ES1n1, ES1n0, ES001, ES000: See 6.3 (4) Prescaler mode register 0n (PRM0n). 2. n = 0, 1 User's Manual U17555EJ3V0UD 153 www..com CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 6.3 Registers Controlling 16-Bit Timer/Event Counters 00 and 01 The following six registers are used to control 16-bit timer/event counters 00 and 01. * 16-bit timer mode control register 0n (TMC0n) * Capture/compare control register 0n (CRC0n) * 16-bit timer output control register 0n (TOC0n) * Prescaler mode register 0n (PRM0n) * Port mode register 0 (PM0) * Port register 0 (P0) (1) 16-bit timer mode control register 0n (TMC0n) This register sets the 16-bit timer operating mode, the 16-bit timer counter 0n (TM0n) clear mode, and output timing, and detects an overflow. 154 User's Manual U17555EJ3V0UD www..com CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Address: FFBAH Symbol TMC00 Figure 6-7. Format of 16-Bit Timer Mode Control Register 00 (TMC00) After reset: 00H 7 0 6 0 R/W 5 0 4 0 3 TMC003 2 TMC002 1 TMC001 <0> OVF00 TMC003 0 TMC002 0 Operation enable of 16-bit timer/event counter 00 Disables 16-bit timer/event counter 00 operation. Stops supplying operating clock. Clears 16-bit timer counter 00 (TM00). 0 1 1 1 0 1 Free-running timer mode Clear & start mode entered by TI000 pin valid edge input Note Clear & start mode entered upon a match between TM00 and CR000 TMC001 0 1 Condition to reverse timer output (TO00) * Match between TM00 and CR000 or match between TM00 and CR010 * Match between TM00 and CR000 or match between TM00 and CR010 * Trigger input of TI000 pin valid edge OVF00 Clear (0) Set (1) TM00 overflow flag Clears OVF00 to 0 or TMC003 and TMC002 = 00 Overflow occurs. OVF00 is set to 1 when the value of TM00 changes from FFFFH to 0000H in all the operation modes (free-running timer mode, clear & start mode entered by TI000 pin valid edge input, and clear & start mode entered upon a match between TM00 and CR000). It can also be set to 1 by writing 1 to OVF00. Note The TI000 pin valid edge is set by bits 5 and 4 (ES001, ES000) of prescaler mode register 00 (PRM00). Remark TO00: 16-bit timer/event counter 00 output pin TI000: 16-bit timer/event counter 00 input pin TM00: 16-bit timer counter 00 CR000: 16-bit timer capture/compare register 000 CR010: 16-bit timer capture/compare register 010 User's Manual U17555EJ3V0UD 155 www..com CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Address: FFB6H Symbol TMC01 Figure 6-8. Format of 16-Bit Timer Mode Control Register 01 (TMC01) After reset: 00H 7 0 6 0 R/W 5 0 4 0 3 TMC013 2 TMC012 1 TMC011 <0> OVF01 TMC013 0 TMC012 0 Operation enable of 16-bit timer/event counter 01 Disables 16-bit timer/event counter 01 operation. Stops supplying operating clock. Clears 16-bit timer counter 01 (TM01). 0 1 1 1 0 1 Free-running timer mode Setting prohibited Clear & start mode entered upon a match between TM01 and CR001 TMC011 0 1 Condition to reverse timer output (TO01) * Match between TM01 and CR001 or match between TM01 and CR011 * Match between TM01 and CR001 or match between TM01 and CR011 OVF01 Clear (0) Set (1) TM01 overflow flag Clears OVF01 to 0 or TMC013 and TMC012 = 00 Overflow occurs. OVF01 is set to 1 when the value of TM01 changes from FFFFH to 0000H in all the operation modes (free-running timer mode and clear & start mode entered upon a match between TM01 and CR001). It can also be set to 1 by writing 1 to OVF01. Remark TO01: 16-bit timer/event counter 01 output pin TM01: 16-bit timer counter 01 CR001: 16-bit timer capture/compare register 001 CR011: 16-bit timer capture/compare register 011 156 User's Manual U17555EJ3V0UD www..com CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (2) Capture/compare control register 0n (CRC0n) Address: FFBCH Symbol CRC00 7 0 n = 0, 1 Figure 6-9. Format of Capture/Compare Control Register 00 (CRC00) After reset: 00H 6 0 R/W 5 0 4 0 3 0 2 CRC002 1 CRC001 0 CRC000 CRC002 0 1 CR010 operating mode selection Operates as compare register Operates as capture register CRC001 0 1 CR000 capture trigger selection Captures on valid edge of TI010 pin Captures on valid edge of TI000 pin by reverse phase Note The valid edge of the TI010 and TI000 pin is set by PRM00. If ES001 and ES000 are set to 11 (both edges) when CRC001 is 1, the valid edge of the TI000 pin cannot be detected. CRC000 0 1 CR000 operating mode selection Operates as compare register Operates as capture register If TMC003 and TMC002 are set to 11 (clear & start mode entered upon a match between TM00 and CR000), be sure to set CRC000 to 0. Note When the valid edge is detected from the TI010 pin, the capture operation is not performed but the INTTM000 signal is generated as an external interrupt signal. Caution To ensure that the capture operation is performed properly, the capture trigger requires a pulse two cycles longer than the count clock selected by prescaler mode register 00 (PRM00). Remark n = 0, 1 User's Manual U17555EJ3V0UD 157 www..com CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 6-10. Example of CR01n Capture Operation (When Rising Edge Is Specified) Valid edge Count clock TM00 TI000 Rising edge detection CR010 INTTM010 N N-3 N-2 N-1 N N+1 Address: FFB8H Symbol CRC01 Figure 6-11. Format of Capture/Compare Control Register 01 (CRC01) After reset: 00H 7 0 6 0 R/W 5 0 4 0 3 0 2 CRC012 Note 1 1 CRC011 Note 2 0 CRC010 Note 1 CRC012 0 1 CR011 operating mode selection Operates as compare register Operates as capture register CRC011 0 1 CR001 capture trigger selection Captures on valid edge of TI011 pin Setting prohibited The valid edge of the TI011 pin is set by PRM01. CRC010 0 1 CR001 operating mode selection Operates as compare register Operates as capture register If TMC013 and TMC012 are set to 11 (clear & start mode entered upon a match between TM01 and CR001), be sure to set CRC010 to 0. Notes 1. 2. Be sure to set to bit 2 and 0 of CRC01 to 0 in PD78F0881, 78F0882 and 78F0883. Be sure to set to bit 1 of CRC01 to 0. Caution To ensure that the capture operation is performed properly, the capture trigger requires a pulse two cycles longer than the count clock selected by prescaler mode register 01 (PRM01) (see Figure 6-10 Example of CR01n Capture Operation (When Rising Edge Is Specified)). 158 User's Manual U17555EJ3V0UD www..com CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (3) 16-bit timer output control register 0n (TOC0n) User's Manual U17555EJ3V0UD 159 www..com CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 6-12. Format of 16-Bit Timer Output Control Register 00 (TOC00) Address: FFBDH Symbol TOC00 7 0 After reset: 00H <6> OSPT00 R/W <5> OSPE00 4 TOC004 <3> LVS00 <2> LVR00 1 TOC001 <0> TOE00 OSPT00 0 1 One-shot pulse output One-shot pulse output trigger via software - The value of this bit is always "0" when it is read. Do not set this bit to 1 in a mode other than the oneshot pulse output mode. If it is set to 1, TM00 is cleared and started. OSPE00 0 1 Successive pulse output One-shot pulse output One-shot pulse output operation control One-shot pulse output operates correctly in the free-running timer mode or clear & start mode entered by TI000 pin valid edge input. The one-shot pulse cannot be output in the clear & start mode entered upon a match between TM00 and CR000. TOC004 0 1 TO00 pin output control on match between CR010 and TM00 Disables inversion operation Enables inversion operation The interrupt signal (INTTM010) is generated even when TOC004 = 0. LVS00 0 0 1 1 LVR00 0 1 0 1 No change Setting of TO00 pin output status Initial value of TO00 pin output is low level (TO00 pin output is cleared to 0). Initial value of TO00 pin output is high level (TO00 pin output is set to 1). Setting prohibited * LVS00 and LVR00 can be used to set the initial value of the output level of the TO00 pin. If the initial value does not have to be set, leave LVS00 and LVR00 as 00. * Be sure to set LVS00 and LVR00 when TOE00 = 1. LVS00, LVR00, and TOE00 being simultaneously set to 1 is prohibited. * LVS00 and LVR00 are trigger bits. By setting these bits to 1, the initial value of the output level of the TO00 pin can be set. Even if these bits are cleared to 0, output of the TO00 pin is not affected. * The values of LVS00 and LVR00 are always 0 when they are read. * For how to set LVS00 and LVR00, see 6.5.2 Setting LVS0n and LVR0n. TOC001 0 1 TO00 pin output control on match between CR000 and TM00 Disables inversion operation Enables inversion operation The interrupt signal (INTTM000) is generated even when TOC001 = 0. TOE00 0 1 TO00 pin output control Disables output (TO00 pin output fixed to low level) Enables output User's Manual U17555EJ3V0UD 160 www..com CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 6-13. Format of 16-Bit Timer Output Control Register 01 (TOC01) Address: FFB9H Symbol TOC01 7 0 OSPT01 0 1 One-shot pulse output After reset: 00H <6> OSPT01 Note R/W <5> OSPE01 Note 4 TOC014 Note <3> LVS01 Note <2> LVR01 Note 1 TOC011 Note <0> TOE01 Note One-shot pulse output trigger via software - The value of this bit is always 0 when it is read. Do not set this bit to 1 in a mode other than the one-shot pulse output mode. If it is set to 1, TM01 is cleared and started. OSPE01 0 1 Successive pulse output One-shot pulse output One-shot pulse output operation control One-shot pulse output operates correctly in the free-running timer mode. The one-shot pulse cannot be output in the clear & start mode entered upon a match between TM01 and CR001. TOC014 0 1 TO01 pin output control on match between CR011 and TM01 Disables inversion operation Enables inversion operation The interrupt signal (INTTM011) is generated even when TOC014 = 0. LVS01 0 0 1 1 LVR01 0 1 0 1 No change Initial value of TO01 pin output is low level (TO01 pin output is cleared to 0). Initial value of TO01 pin output is high level (TO01 pin output is set to 1). Setting prohibited Setting of TO01 pin output status * LVS01 and LVR01 can be used to set the initial value of the output level of the TO01 pin. If the initial value does not have to be set, leave LVS01 and LVR01 as 00. * Be sure to set LVS01 and LVR01 when TOE01 = 1. LVS01, LVR01, and TOE01 being simultaneously set to 1 is prohibited. * LVS01 and LVR01 are trigger bits. By setting these bits to 1, the initial value of the output level of the TO01 pin can be set. Even if these bits are cleared to 0, output of the TO01 pin is not affected. * The values of LVS01 and LVR01 are always 0 when they are read. * For how to set LVS01 and LVR01, see 6.5.2 Setting LVS0n and LVR0n. TOC011 0 1 TO01 pin output control on match between CR001 and TM01 Disables inversion operation Enables inversion operation The interrupt signal (INTTM001) is generated even when TOC011 = 0. TOE01 0 1 TO01 pin output control Disables output (TO01 pin output is fixed to low level) Enables output Note Be sure to set to bit 6 to 0 of TOC01 to 0 in PD78F0881, 78F0882 and 78F0883. User's Manual U17555EJ3V0UD 161 www..com CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (4) Prescaler mode register 0n (PRM0n) 162 User's Manual U17555EJ3V0UD www..com CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 6-14. Format of Prescaler Mode Register 00 (PRM00) Address: FFBBH Symbol PRM00 7 ES101 After reset: 00H 6 ES100 R/W 5 ES001 4 ES000 3 0 2 0 1 PRM001 0 PRM000 ES101 0 0 1 1 ES100 0 1 0 1 Falling edge Rising edge Setting prohibited TI010 pin valid edge selection Both falling and rising edges ES001 0 0 1 1 ES000 0 1 0 1 Falling edge Rising edge Setting prohibited TI000 pin valid edge selection Both falling and rising edges PRM001 PRM000 Count clock selection fPRS = 4 MHz fPRS = 5 MHz 5 MHz 312.5 kHz 78.125 kHz fPRS = 10 MHz 10 MHz 625 kHz 156.25 kHz fPRS = 20 MHz 20 MHz 1.25 MHz 312.5 kHz 0 0 1 0 1 fPRS fPRS/2 fPRS/2 4 4 MHz 250 kHz 62.5 kHz Note 0 1 1 6 TI000 valid edge Note The external clock requires a pulse two cycles longer than internal clock (fPRS). Cautions 1. Always set data to PRM00 after stopping the timer operation. 2. If the valid edge of the TI000 pin is to be set for the count clock, do not set the clear & start mode using the valid edge of the TI000 pin and the capture trigger. 3. If the TI000 or TI010 pin is high level immediately after system reset, the rising edge is immediately detected after the rising edge or both the rising and falling edges are set as the valid edge(s) of the TI000 pin or TI010 pin to enable the operation of 16-bit timer counter 00 (TM00). Care is therefore required when pulling up the TI000 or TI010 pin. However, when re-enabling operation for TI000 pin or TI010 pin are high level after the operation has been stopped, the rising edge is not detected. 4. When TI010 pin is used valid edge, it cannot be used as the timer output (TO00) to P01, and when TO00 is used, it cannot be used to the TI010 pin valid edge. Remark fPRS: Peripheral hardware clock frequency User's Manual U17555EJ3V0UD 163 www..com CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 6-15. Format of Prescaler Mode Register 01 (PRM01) Address: FFB7H Symbol PRM01 7 ES111 Note After reset: 00H 6 ES110 Note R/W 5 0 4 0 3 0 2 0 1 PRM011 0 PRM010 ES111 0 0 1 1 ES110 0 1 0 1 Falling edge Rising edge Setting prohibited TI011 pin valid edge selection Both falling and rising edges PRM011 PRM010 Count clock selection fPRS = 4 MHz fPRS = 5 MHz 5 MHz 1.25 MHz 19.53 kHz fPRS = 10 MHz 10 MHz 2.5 MHz 39.06 kHz fPRS = 20 MHz 20 MHz 5 MHz 78.12 kHz 0 0 1 1 0 1 0 1 fPRS fPRS/2 fPRS/2 2 4 MHz 1 MHz 15.62 kHz 8 Setting prohibited Note Be sure to set to bit 7 and 6 of PRM01 to 0 in PD78F0881, 78F0882 and 78F0883. Cautions 1. Always set data to PRM01 after stopping the timer operation. 2. If the TI011 pin is high level immediately after system reset, the rising edge is immediately detected after the rising edge or both the rising and falling edges are set as the valid edge(s) of the TI011 pin to enable the operation of 16-bit timer counter 01 (TM01). Care is therefore required when pulling up the TI011 pin. However, when re-enabling operation for TI011 pin are high level after the operation has been stopped, the rising edge is not detected. 3. When TI011 pin is used valid edge, it cannot be used as the timer output (TO01) to P06, and when TO01 is used, it cannot be used to the TI011 pin valid edge. Remark fPRS: Peripheral hardware clock frequency 164 User's Manual U17555EJ3V0UD www..com CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (5) Port mode register 0 (PM0) This register sets port 0 input/output in 1-bit units. When using the P01/TO00/TI010 and P06/TO01/TI011 pin for timer output, set PM01, PM06, the output latch of P01 and P06 to 0. When using the P01/TO00/TI010 and P06/TO01/TI011 pin for timer input, set PM01 and PM06 to 1. At this time, the output latch of P01 and P06 may be 0 or 1. PM0 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets PM0 to FFH. Figure 6-16. Format of Port Mode Register 0 (PM0) Address: FF14H Symbol PM0 7 1 After reset: FFH 6 PM06 Note R/W 5 1 4 1 3 1 2 1 1 PM01 0 PM00 PM0n 0 1 P0n pin I/O mode selection (n = 0, 1, 6) Output mode (Output buffer on) Input mode (Output buffer off) Note PD78F0884, 78F0885, 78F0886 only. User's Manual U17555EJ3V0UD 165 www..com CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 6.4 Operation of 16-Bit Timer/Event Counters 00 and 01 6.4.1 Interval timer operation Setting 16-bit timer mode control register 0n (TMC0n) and capture/compare control register 0n (CRC0n) as shown in Figure 6-17 allows operation as an interval timer. Setting The basic operation setting procedure is as follows. <1> Set the CRC0n register (see Figure 6-17 for the set value). <2> Set any value to the CR00n register. <3> Set the count clock by using the PRM0n register. <4> Set the TMC0n register to start the operation (see Figure 6-17 for the set value). Caution CR00n cannot be rewritten during TM0n operation. Remark For how to enable the INTTM00n interrupt, see CHAPTER 16 INTERRUPT FUNCTIONS. Interrupt requests are generated repeatedly using the count value preset in 16-bit timer capture/compare register 00n (CR00n) as the interval. When the count value of 16-bit timer counter 0n (TM0n) matches the value set in CR00n, counting continues with the TM0n value cleared to 0 and the interrupt request signal (INTTM00n) is generated. The count clock of 16-bit timer/event counter 0n can be selected with bits 0 and 1 (PRM0n0, PRM0n1) of prescaler mode register 0n (PRM0n). Remark n = 0, 1 166 User's Manual U17555EJ3V0UD www..com CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 6-17. Control Register Settings for Interval Timer Operation (a) 16-bit timer mode control register 0n (TMC0n) 7 TMC0n 0 6 0 5 0 4 0 TMC0n3 TMC0n2 TMC0n1 OVF0n 1 1 0/1 0 Clears and starts on match between TM0n and CR00n. (b) Capture/compare control register 0n (CRC0n) 7 CRC0n 0 6 0 5 0 4 0 3 0 CRC0n2 CRC0n1 CRC0n0 0/1 0/1 0 CR00n used as compare register (c) Prescaler mode register 0n (PRM0n) Note Note ES1n1 ES1n0 ES001 ES000 PRM0n 0/1 0/1 0/1 0/1 3 0 2 0 PRM0n1 PRM0n0 0/1 0/1 Selects count clock. Setting invalid (setting "10" is prohibited.) Setting invalid (setting "10" is prohibited.) Note PRM00 only. Be sure to set to 0 in PRM01 Remarks 1. 0/1: Setting 0 or 1 allows another function to be used simultaneously with the interval timer. See the description of the respective control registers for details. 2. n = 0, 1 User's Manual U17555EJ3V0UD 167 www..com CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 6-18. Interval Timer Configuration Diagram 16-bit timer capture/compare register 00n (CR00n) INTTM00n fPRS fPRS/22 fPRS/28 TI000/P00 Noise eliminator Selector 16-bit timer counter 0n (TM0n) Note OVF0n Clear circuit fPRS Note OVF0n is set to 1 only when 16-bit timer capture/compare register 00n is set to FFFFH. Figure 6-19. Timing of Interval Timer Operation t Count clock TM0n count value 0000H 0001H N 0000H 0001H Clear N N 0000H 0001H Clear N N N Timer operation enabled CR00n INTTM00n N Interrupt acknowledged Interrupt acknowledged Remark Interval time = (N + 1) x t N = 0001H to FFFFH n = 0, 1 168 User's Manual U17555EJ3V0UD www..com CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 6.4.2 PPG output operations Setting 16-bit timer mode control register 0n (TMC0n) and capture/compare control register 0n (CRC0n) as shown in Figure 6-20 allows operation as PPG (Programmable Pulse Generator) output. Setting The basic operation setting procedure is as follows. <1> Set the CRC0n register (see Figure 6-20 for the set value). <2> Set any value to the CR00n register as the cycle. <3> Set any value to the CR01n register as the duty factor. <4> Set the TOC0n register (see Figure 6-20 for the set value). <5> Set the count clock by using the PRM0n register. <6> Set the TMC0n register to start the operation (see Figure 6-20 for the set value). Caution To change the value of the duty factor (the value of the CR01n register) during operation, see Caution 2 in Figure 6-22 PPG Output Operation Timing. Remarks 1. For the setting of the TO0n pin, see 6.3 (5) Port mode register 0 (PM0). 2. For how to enable the INTTM00n interrupt, see CHAPTER 16 INTERRUPT FUNCTIONS. In the PPG output operation, rectangular waves are output from the TO0n pin with the pulse width and the cycle that correspond to the count values preset in 16-bit timer capture/compare register 01n (CR01n) and in 16-bit timer capture/compare register 00n (CR00n), respectively. Remark n = 0, 1 User's Manual U17555EJ3V0UD 169 www..com CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 6-20. Control Register Settings for PPG Output Operation (a) 16-bit timer mode control register 0n (TMC0n) 7 TMC0n 0 6 0 5 0 4 0 TMC0n3 TMC0n2 TMC0n1 OVF0n 1 1 0 0 Clears and starts on match between TM0n and CR00n. (b) Capture/compare control register 0n (CRC0n) 7 CRC0n 0 6 0 5 0 4 0 3 0 CRC0n2 CRC0n1 CRC0n0 0 x 0 CR00n used as compare register CR01n used as compare register (c) 16-bit timer output control register 0n (TOC0n) 7 TOC0n 0 OSPT0n OSPE0n TOC0n4 LVS0n LVR0n TOC0n1 TOE0n 0 0 1 0/1 0/1 1 1 Enables TO0n output. Inverts output on match between TM0n and CR00n. Specifies initial value of TO0n output F/F (setting "11" is prohibited). Inverts output on match between TM0n and CR01n. Disables one-shot pulse output. (d) Prescaler mode register 0n (PRM0n) ES1n1 ES1n0 ES001 ES000 PRM0n 0/1 0/1 0/1 0/1 Note Note 3 0 2 0 PRM0n1 PRM0n0 0/1 0/1 Selects count clock. Setting invalid (setting "10" is prohibited.) Setting invalid (setting "10" is prohibited.) Note PRM00 only. Be sure to set to 0 in PRM01 Cautions 1. Values in the following range should be set in CR00n and CR01n: 0000H CR01n < CR00n FFFFH 2. The cycle of the pulse generated through PPG output (CR00n setting value + 1) has a duty of (CR01n setting value + 1)/(CR00n setting value + 1). Remark x: Don't care n = 0, 1 170 User's Manual U17555EJ3V0UD www..com CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 6-21. Configuration Diagram of PPG Output 16-bit timer capture/compare register 00n (CR00n) fPRS fPRS/22 fPRS/28 TI000/P00 Noise eliminator fPRS Selector 16-bit timer counter 0n (TM0n) Clear circuit Output controller TO00/TI010/P01 16-bit timer capture/compare register 01n (CR01n) Figure 6-22. PPG Output Operation Timing t Count clock TM0n count value N 0000H 0001H M-1 M N-1 N 0000H 0001H Clear CR00n capture value CR01n capture value TO0n Pulse width: (M + 1) x t 1 cycle: (N + 1) x t N M Clear Cautions 1. CR00n cannot be rewritten during TM0n operation. 2. In the PPG output operation, change the pulse width (rewrite CR01n) during TM0n operation using the following procedure. <1> Disable the timer output inversion operation by match of TM0n and CR01n (TOC0n4 = 0) <2> Disable the INTTM01n interrupt (TMMK01n = 1) <3> Rewrite CR01n <4> Wait for 1 cycle of the TM0n count clock <5> Enable the timer output inversion operation by match of TM0n and CR01n (TOC0n4 = 1) <6> Clear the interrupt request flag of INTTM01n (TMIF01n = 0) <7> Enable the INTTM01n interrupt (TMMK01n = 0) Remarks 1. 0000H M < N FFFFH 2. n = 0, 1 User's Manual U17555EJ3V0UD 171 www..com CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 6.4.3 Pulse width measurement operations Pulse width measurement is using for16-bit timer counter 00 (TM00) only. It is possible to measure the pulse width of the signals input to the TI000 pin using 16-bit timer counter 00 (TM00). There are two measurement methods: measuring with TM00 used in free-running mode, and measuring by restarting the timer in synchronization with the edge of the signal input to the TI000 pin. When an interrupt occurs, read the valid value of the capture register, check the overflow flag, and then calculate the necessary pulse width. Clear the overflow flag after checking it. The capture operation is not performed until the signal pulse width is sampled in the count clock cycle selected by prescaler mode register 0n (PRM0n) and the valid level of the TI000 or TI010 pin is detected twice, thus eliminating noise with a short pulse width. Figure 6-23. CR010 Capture Operation with Rising Edge Specified Count clock TM00 TI000 Rising edge detection CR010 INTTM010 N N-3 N-2 N-1 N N+1 Setting The basic operation setting procedure is as follows. <1> Set the CRC00 register (see Figures 6-24, 6-27, 6-29, and 6-31 for the set value). <2> Set the count clock by using the PRM00 register. <3> Set the TMC00 register to start the operation (see Figures 6-24, 6-27, 6-29, and 6-31 for the set value). Caution To use two capture registers, set the TI000 and TI010 pins. Remarks 1. 2. For the setting of the TI000 (or TI010) pin, see 6.3 (5) Port mode register 0 (PM0). For how to enable the INTTM000 (or INTTM010) interrupt, see CHAPTER 16 FUNCTIONS. INTERRUPT 172 User's Manual U17555EJ3V0UD www..com CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (1) Pulse width measurement with free-running counter and one capture register When 16-bit timer counter 00 (TM00) is operated in free-running mode, and the edge specified by prescaler mode register 00 (PRM00) is input to the TI000 pin, the value of TM00 is taken into 16-bit timer capture/compare register 010 (CR010) and an external interrupt request signal (INTTM010) is set. Specify both the rising and falling edges of the TI000 pin by using bits 4 and 5 (ES000 and ES001) of PRM00. Sampling is performed using the count clock selected by PRM00, and a capture operation is only performed when a valid level of the TI000 pin is detected twice, thus eliminating noise with a short pulse width. Figure 6-24. Control Register Settings for Pulse Width Measurement with Free-Running Counter and One Capture Register (When TI000 and CR010 Are Used) (a) 16-bit timer mode control register 00 (TMC00) 7 TMC00 0 6 0 5 0 4 0 TMC003 TMC002 TMC001 OVF00 0 1 0/1 0 Free-running mode (b) Capture/compare control register 00 (CRC00) 7 CRC00 0 6 0 5 0 4 0 3 0 CRC002 CRC001 CRC000 1 0/1 0 CR000 used as compare register CR010 used as capture register (c) Prescaler mode register 00 (PRM00) ES101 ES100 ES001 ES000 PRM00 0/1 0/1 1 1 3 0 2 0 PRM001 PRM000 0/1 0/1 Selects count clock (setting "11" is prohibited). Specifies both edges for pulse width detection. Setting invalid (setting "10" is prohibited.) Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with pulse width measurement. See the description of the respective control registers for details. User's Manual U17555EJ3V0UD 173 www..com CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 6-25. Configuration Diagram for Pulse Width Measurement with Free-Running Counter fPRS Selector fPRS/22 fPRS/28 16-bit timer counter 0n (TM00) OVF00 TI000 16-bit timer capture/compare register 010 (CR010) INTTM010 Internal bus Figure 6-26. Timing of Pulse Width Measurement Operation with Free-Running Counter and One Capture Register (with Both Edges Specified) t Count clock TM00 count value TI000 pin input CR010 capture value INTTM010 OVF00 (D1 - D0) x t (10000H - D1 + D2) x t Note (D3 - D2) x t D0 D1 D2 D3 0000H 0001H D0 D0 + 1 D1 D1 + 1 FFFFH 0000H D2 D3 Note Clear OVF0n by software. 174 User's Manual U17555EJ3V0UD www..com CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (2) Measurement of two pulse widths with free-running counter When 16-bit timer counter 00 (TM00) is operated in free-running mode, it is possible to simultaneously measure the pulse widths of the two signals input to the TI000 pin and the TI010 pin. When the edge specified by bits 4 and 5 (ES000 and ES001) of prescaler mode register 00 (PRM00) is input to the TI000 pin, the value of TM00 is taken into 16-bit timer capture/compare register 010 (CR010) and an interrupt request signal (INTTM010) is set. Also, when the edge specified by bits 6 and 7 (ES100 and ES101) of PRM00 is input to the TI010 pin, the value of TM00 is taken into 16-bit timer capture/compare register 000 (CR000) and an interrupt request signal (INTTM000) is set. Specify both the rising and falling edges as the edges of the TI000 and TI010 pins, by using bits 4 and 5 (ES000 and ES001) and bits 6 and 7 (ES100 and ES101) of PRM00. Sampling is performed using the count clock cycle selected by prescaler mode register 00 (PRM00), and a capture operation is only performed when a valid level of the TI000 or TI010 pin is detected twice, thus eliminating noise with a short pulse width. Figure 6-27. Control Register Settings for Measurement of Two Pulse Widths with Free-Running Counter (a) 16-bit timer mode control register 00 (TMC00) 7 TMC00 0 6 0 5 0 4 0 TMC003 TMC002 TMC001 OVF00 0 1 0/1 0 Free-running mode (b) Capture/compare control register 0n (CRC00) 7 CRC00 0 6 0 5 0 4 0 3 0 CRC002 CRC001 CRC000 1 0 1 CR000 used as capture register Captures valid edge of TI010 pin to CR000. CR010 used as capture register (c) Prescaler mode register 0n (PRM00) ES101 ES100 ES001 ES000 PRM00 1 1 1 1 3 0 2 0 PRM001 PRM000 0/1 0/1 Selects count clock (setting "11" is prohibited). Specifies both edges for pulse width detection. Specifies both edges for pulse width detection. Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with pulse width measurement. See the description of the respective control registers for details. User's Manual U17555EJ3V0UD 175 www..com CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 6-28. Timing of Pulse Width Measurement Operation with Free-Running Counter (with Both Edges Specified) t Count clock TM00 count value TI000 pin input CR010 capture value INTTM010 TI010 pin input CR000 capture value INTTM000 OVF00 Note D1 D2 + 1 D0 D1 D2 0000H 0001H D0 D0 + 1 D1 D1 + 1 FFFFH 0000H D2 D2 + 1 D2 + 2 D3 (D1 - D0) x t (10000H - D1 + D2) x t (D3 - D2) x t (10000H - D1 + (D2 + 1)) x t Note Clear OVF0n by software. 176 User's Manual U17555EJ3V0UD www..com CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (3) Pulse width measurement with free-running counter and two capture registers When 16-bit timer counter 00 (TM00) is operated in free-running mode, it is possible to measure the pulse width of the signal input to the TI000 pin. When the rising or falling edge specified by bits 4 and 5 (ES000 and ES001) of prescaler mode register 00 (PRM00) is input to the TI000 pin, the value of TM00 is taken into 16-bit timer capture/compare register 010 (CR010) and an interrupt request signal (INTTM010) is set. Also, when the inverse edge to that of the capture operation is input into CR010, the value of TM00 is taken into 16-bit timer capture/compare register 000 (CR000). Sampling is performed using the count clock cycle selected by prescaler mode register 00 (PRM00), and a capture operation is only performed when a valid level of the TI000 pin is detected twice, thus eliminating noise with a short pulse width. Figure 6-29. Control Register Settings for Pulse Width Measurement with Free-Running Counter and Two Capture Registers (with Rising Edge Specified) (a) 16-bit timer mode control register 00 (TMC00) 7 TMC00 0 6 0 5 0 4 0 TMC003 TMC002 TMC001 OVF00 0 1 0/1 0 Free-running mode (b) Capture/compare control register 00 (CRC00) 7 CRC00 0 6 0 5 0 4 0 3 0 CRC002 CRC001 CRC000 1 1 1 CR000 used as capture register Captures to CR000 at inverse edge to valid edge of TI000. CR010 used as capture register (c) Prescaler mode register 00 (PRM00) ES101 ES100 ES001 ES000 PRM00 0/1 0/1 0 1 3 0 2 0 PRM001 PRM000 0/1 0/1 Selects count clock (setting "11" is prohibited). Specifies rising edge for pulse width detection. Setting invalid (setting "10" is prohibited.) Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with pulse width measurement. See the description of the respective control registers for details. User's Manual U17555EJ3V0UD 177 www..com CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 6-30. Timing of Pulse Width Measurement Operation with Free-Running Counter and Two Capture Registers (with Rising Edge Specified) t Count clock TM00 count value TI000 pin input CR010 capture value CR000 capture value INTTM010 OVF00 (D1 - D0) x t (10000H - D1 + D2) x t Note (D3 - D2) x t D0 D1 D2 D3 0000H 0001H D0 D0 + 1 D1 D1 + 1 FFFFH 0000H D2 D2 + 1 D3 Note Clear OVF00 by software. (4) Pulse width measurement by means of restart When input of a valid edge to the TI000 pin is detected, the count value of 16-bit timer counter 00 (TM00) is taken into 16-bit timer capture/compare register 010 (CR010), and then the pulse width of the signal input to the TI000 pin is measured by clearing TM00 and restarting the count operation. Either of two edgesrising or fallingcan be selected using bits 4 and 5 (ES000 and ES001) of prescaler mode register 00 (PRM00). Sampling is performed using the count clock cycle selected by prescaler mode register 00 (PRM00) and a capture operation is only performed when a valid level of the TI000 pin is detected twice, thus eliminating noise with a short pulse width. 178 User's Manual U17555EJ3V0UD www..com CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 6-31. Control Register Settings for Pulse Width Measurement by Means of Restart (with Rising Edge Specified) (a) 16-bit timer mode control register 00 (TMC00) 7 TMC00 0 6 0 5 0 4 0 TMC003 TMC002 TMC001 OVF00 1 0 0/1 0 Clears and starts at valid edge of TI000 pin. (b) Capture/compare control register 00 (CRC00) 7 CRC00 0 6 0 5 0 4 0 3 0 CRC002 CRC001 CRC000 1 1 1 CR000 used as capture register Captures to CR000 at inverse edge to valid edge of TI000. CR010 used as capture register (c) Prescaler mode register 00 (PRM00) ES101 ES100 ES001 ES000 PRM00 0/1 0/1 0 1 3 0 2 0 PRM001 PRM000 0/1 0/1 Selects count clock (setting "11" is prohibited). Specifies rising edge for pulse width detection. Setting invalid (setting "10" is prohibited.) Figure 6-32. Timing of Pulse Width Measurement Operation by Means of Restart (with Rising Edge Specified) t Count clock TM00 count value TI000 pin input CR010 capture value CR000 capture value INTTM010 D1 x t D2 x t D0 D1 D2 0000H 0001H D0 0000H 0001H D1 D2 0000H 0001H User's Manual U17555EJ3V0UD 179 www..com CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 6.4.4 External event counter operation This function is using for16-bit timer counter 00 (TM00) only. Setting The basic operation setting procedure is as follows. <1> Set the CRC00 register (see Figure 6-33 for the set value). <2> Set the count clock by using the PRM00 register. <3> Set any value to the CR000 register (0000H cannot be set). <4> Set the TMC00 register to start the operation (see Figure 6-33 for the set value). Remarks 1. For the setting of the TI000 pin, see 6.3 (5) Port mode register 0 (PM0). 2. For how to enable the INTTM000 interrupt, see CHAPTER 16 INTERRUPT FUNCTIONS. The external event counter counts the number of external clock pulses input to the TI000 pin using 16-bit timer counter 00 (TM00). TM00 is incremented each time the valid edge specified by prescaler mode register 00 (PRM00) is input. When the TM00 count value matches the 16-bit timer capture/compare register 000 (CR000) value, TM00 is cleared to 0 and the interrupt request signal (INTTM000) is generated. Input a value other than 0000H to CR000 (a count operation with 1-bit pulse cannot be carried out). Any of three edgesrising, falling, or both edgescan be selected using bits 4 and 5 (ES000 and ES001) of prescaler mode register 00 (PRM00). Sampling is performed using the internal clock (fPRS) and an operation is only performed when a valid level of the TI000 pin is detected twice, thus eliminating noise with a short pulse width. 180 User's Manual U17555EJ3V0UD www..com CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 6-33. Control Register Settings in External Event Counter Mode (with Rising Edge Specified) (a) 16-bit timer mode control register 00 (TMC00) 7 TMC00 0 6 0 5 0 4 0 TMC003 TMC002 TMC001 OVF000 1 1 0/1 Clears and starts on match between TM00 and CR000. (b) Capture/compare control register 00 (CRC00) 7 CRC00 0 6 0 5 0 4 0 3 0 CRC002 CRC001 CRC000 0/1 0/1 0 CR000 used as compare register (c) Prescaler mode register 00 (PRM00) ES101 ES100 ES001 ES000 PRM00 0/1 0/1 0 1 3 0 2 0 PRM001 PRM000 1 1 Selects external clock. Specifies rising edge for pulse width detection. Setting invalid (setting "10" is prohibited.) Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with the external event counter. See the description of the respective control registers for details. User's Manual U17555EJ3V0UD 181 www..com CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 6-34. Configuration Diagram of External Event Counter Internal bus 16-bit timer capture/compare register 000 (CR000) Match INTTM000 Clear Valid edge of TI000 pin Noise eliminator 16-bit timer counter 00 (TM00) OVF00Note fPRS Note OVF00 is set to 1 only when CR000 is set to FFFFH. Figure 6-35. External Event Counter Operation Timing (with Rising Edge Specified) TI000 pin input TM00 count value CR000 INTTM000 0000H 0001H 0002H 0003H 0004H 0005H N N-1 N 0000H 0001H 0002H 0003H Caution When reading the external event counter count value, TM00 should be read. 182 User's Manual U17555EJ3V0UD www..com CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 6.4.5 Square-wave output operation Setting The basic operation setting procedure is as follows. <1> Set the count clock by using the PRM0n register. <2> Set the CRC0n register (see Figure 6-36 for the set value). <3> Set the TOC0n register (see Figure 6-36 for the set value). <4> Set any value to the CR00n register (0000H cannot be set). <5> Set the TMC0n register to start the operation (see Figure 6-36 for the set value). Caution CR00n cannot be rewritten during TM0n operation. Remarks 1. For the setting of the TO0n pin, see 6.3 (5) Port mode register 0 (PM0). 2. For how to enable the INTTM00n interrupt, see CHAPTER 16 INTERRUPT FUNCTIONS. A square wave with any selected frequency can be output at intervals determined by the count value preset to 16bit timer capture/compare register 00n (CR00n). The TO0n pin output status is reversed at intervals determined by the count value preset to CR00n + 1 by setting bit 0 (TOE0n) and bit 1 (TOC0n1) of 16-bit timer output control register 0n (TOC0n) to 1. This enables a square wave with any selected frequency to be output. Figure 6-36. Control Register Settings in Square-Wave Output Mode (1/2) (a) 16-bit timer mode control register 0n (TMC0n) 7 TMC0n 0 6 0 5 0 4 0 TMC0n3 TMC0n2 TMC0n1 OVF0n 1 1 0 0 Clears and starts on match between TM0n and CR00n. (b) Capture/compare control register 0n (CRC0n) 7 CRC0n 0 6 0 5 0 4 0 3 0 CRC0n2 CRC0n1 CRC0n0 0/1 0/1 0 CR00n used as compare register User's Manual U17555EJ3V0UD 183 www..com CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 6-36. Control Register Settings in Square-Wave Output Mode (2/2) (c) 16-bit timer output control register 0n (TOC0n) 7 TOC0n 0 OSPT0n OSPE0n TOC0n4 LVS0n LVR0n TOC0n1 TOE0n 0 0 0 0/1 0/1 1 1 Enables TO0n output. Inverts output on match between TM0n and CR00n. Specifies initial value of TO0n output F/F (setting "11" is prohibited). Does not invert output on match between TM0n and CR01n. Disables one-shot pulse output. (d) Prescaler mode register 0n (PRM0n) Note Note ES1n1 ES1n0 ES001 ES000 PRM0n 0/1 0/1 0/1 0/1 3 0 2 0 PRM0n1 PRM0n0 0/1 0/1 Selects count clock. Setting invalid (setting "10" is prohibited.) Setting invalid (setting "10" is prohibited.) Note PRM00 only. Be sure to set to 0 in PRM01 Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with square-wave output. See the description of the respective control registers for details. n = 0, 1 Figure 6-37. Square-Wave Output Operation Timing Count clock TM0n count value CR00n INTTM00n TO0n pin output 0000H 0001H 0002H N N-1 N 0000H 0001H 0002H N-1 N 0000H Remark n = 0, 1 184 User's Manual U17555EJ3V0UD www..com CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 6.4.6 One-shot pulse output operation 16-bit timer/event counter 0n can output a one-shot pulse in synchronization with a software trigger or an external trigger (TI000 pin input). Setting The basic operation setting procedure is as follows. <1> Set the count clock by using the PRM0n register. <2> Set the CRC0n register (see Figures 6-38 and 6-40 for the set value). <3> Set the TOC0n register (see Figures 6-38 and 6-40 for the set value). <4> Set any value to the CR00n and CR01n registers (0000H cannot be set). <5> Set the TMC0n register to start the operation (see Figures 6-38 and 6-40 for the set value). Remarks 1. For the setting of the TO0n pin, see 6.3 (5) Port mode register 0 (PM0) and (6) Port mode register 3 (PM3). 2. For how to enable the INTTM00n (if necessary, INTTM01n) interrupt, see CHAPTER 16 INTERRUPT FUNCTIONS. (1) One-shot pulse output with software trigger A one-shot pulse can be output from the TO0n pin by setting 16-bit timer mode control register 0n (TMC0n), capture/compare control register 0n (CRC0n), and 16-bit timer output control register 0n (TOC0n) as shown in Figure 6-38, and by setting bit 6 (OSPT0n) of the TOC0n register to 1 by software. By setting the OSPT0n bit to 1, 16-bit timer/event counter 0n is cleared and started, and its output becomes active at the count value (N) set in advance to 16-bit timer capture/compare register 01n (CR01n). After that, the output becomes inactive at the count value (M) set in advance to 16-bit timer capture/compare register 00n (CR00n)Note. Even after the one-shot pulse has been output, the TM0n register continues its operation. To stop the TM0n register, the TMC0n3 and TMC0n2 bits of the TMC0n register must be set to 00. Note The case where N < M is described here. When N > M, the output becomes active with the CR00n register and inactive with the CR01n register. Do not set N to M. Cautions 1. 2. Do not set the OSPT0n bit while the one-shot pulse is being output. To output the oneshot pulse again, wait until the current one-shot pulse output is completed. When using the one-shot pulse output of 16-bit timer/event counter 0n with a software trigger, do not change the level of the TI000 pin or its alternate-function port pin. Because the external trigger is valid even in this case, the timer is cleared and started even at the level of the TI000 pin or its alternate-function port pin, resulting in the output of a pulse at an undesired timing. Remark n = 0, 1 User's Manual U17555EJ3V0UD 185 www..com CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 6-38. Control Register Settings for One-Shot Pulse Output with Software Trigger (a) 16-bit timer mode control register 0n (TMC0n) 7 TMC0n 0 6 0 5 0 4 0 TMC0n3 TMC0n2 TMC0n1 0 1 0 OVF0n 0 Free-running mode (b) Capture/compare control register 0n (CRC0n) 7 CRC0n 0 6 0 5 0 4 0 3 0 CRC0n2 CRC0n1 CRC0n0 0 0/1 0 CR00n as compare register CR01n as compare register (c) 16-bit timer output control register 0n (TOC0n) 7 TOC0n 0 OSPT0n OSPE0n TOC0n4 0 1 1 LVS0n 0/1 LVR0n 0/1 TOC0n1 1 TOE0n 1 Enables TO0n output. Inverts output upon match between TM0n and CR00n. Specifies initial value of TO0n output F/F (setting "11" is prohibited.) Inverts output upon match between TM0n and CR01n. Sets one-shot pulse output mode. Set to 1 for output. (d) Prescaler mode register 0n (PRM0n) ES1n1 PRM0n 0/1 ES1n0 0/1 ES001 0/1 Note ES000 0/1 Note 3 0 2 0 PRM0n1 PRM0n0 0/1 0/1 Selects count clock. Setting invalid (setting "10" is prohibited.) Setting invalid (setting "10" is prohibited.) Note PRM00 only. Be sure to set to 0 in PRM01 Caution Do not set 0000H to the CR00n and CR01n registers. Remark n = 0, 1 User's Manual U17555EJ3V0UD 186 www..com CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 6-39. Timing of One-Shot Pulse Output Operation with Software Trigger Set TMC0n to 04H (TM0n count starts) Count clock TM0n count 0000H 0001H CR01n set value CR00n set value OSPT0n INTTM01n INTTM00n TO0n pin output N M N N+1 N M 0000H N-1 N N M M-1 M M+1 M+2 N M Caution 16-bit timer counter 0n starts operating as soon as a value other than 00 (operation stop mode) is set to the TMC0n3 and TMC0n2 bits. Remark N User's Manual U17555EJ3V0UD 187 www..com CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 6-40. Control Register Settings for One-Shot Pulse Output with External Trigger (with Rising Edge Specified) (a) 16-bit timer mode control register 00 (TMC00) 7 TMC00 0 6 0 5 0 4 0 TMC003 TMC002 TMC001 1 0 0 OVF00 0 Clears and starts at valid edge of TI000 pin. (b) Capture/compare control register 00 (CRC00) 7 CRC00 0 6 0 5 0 4 0 3 0 CRC002 CRC001 CRC000 0 0/1 0 CR000 used as compare register CR010 used as compare register (c) 16-bit timer output control register 00 (TOC00) 7 TOC00 0 OSPT00 OSPE00 TOC004 0 1 1 LVS00 0/1 LVR00 0/1 TOC001 1 TOE00 1 Enables TO00 output. Inverts output upon match between TM00 and CR000. Specifies initial value of TO00 output F/F (setting "11" is prohibited.) Inverts output upon match between TM00 and CR010. Sets one-shot pulse output mode. (d) Prescaler mode register 00 (PRM00) ES101 PRM00 0/1 ES100 0/1 ES001 0 ES000 1 3 0 2 0 PRM001 PRM000 0/1 0/1 Selects count clock (setting "11" is prohibited). Specifies the rising edge for pulse width detection. Setting invalid (setting "10" is prohibited.) Caution Do not set the CR000 and CR010 registers to 0000H. 188 User's Manual U17555EJ3V0UD www..com CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 6-41. Timing of One-Shot Pulse Output Operation with External Trigger (with Rising Edge Specified) When TMC00 is set to 08H (TM00 count starts) t Count clock TM00 count value 0000H 0001H CR010 set value CR000 set value TI000 pin input INTTM010 INTTM000 TO00 pin output N M 0000H N M N N+1 N+2 N M M-2 M-1 M N M M+1 M+2 Caution 16-bit timer counter 00 starts operating as soon as a value other than 00 (operation stop mode) is set to the TMC002 and TMC003 bits. Remark N 189 www..com CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 6.5.2 Setting LVS0n and LVR0n (1) Usage of LVS0n and LVR0n LVS0n and LVR0n are used to set the default value of the TO0n pin output and to invert the timer output without enabling the timer operation (TMC0n3 and TMC0n2 = 00). Clear LVS0n and LVR0n to 00 (default value: lowlevel output) when software control is unnecessary. LVS0n 0 0 1 1 LVR0n 0 1 0 1 Timer Output Status Not changed (low-level output) Cleared (low-level output) Set (high-level output) Setting prohibited Remark n = 0, 1 190 User's Manual U17555EJ3V0UD www..com CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (2) Setting LVS0n and LVR0n Set LVS0n and LVR0n using the following procedure. Figure 6-42. Example of Flow for Setting LVS0n and LVR0n Bits Setting TOC0n.OSPE0n, TOC0n4, TOC0n1 bits <1> Setting of timer output operation Setting TOC0n.TOE0n bit Setting TOC0n.LVS0n, LVR0n bits Setting TMC0n.TMC0n3, TMC0n2 bits <2> Setting of timer output F/F <3> Enabling timer operation Caution Be sure to set LVS0n and LVR0n following steps <1>, <2>, and <3> above. Step <2> can be performed after <1> and before <3>. Figure 6-43. Timing Example of LVR0n and LVS0n TOC0n.LVS0n bit TOC0n.LVR0n bit Operable bits (TMC0n3, TMC0n2) TO0n pin output INTTM00n signal <1> <2> <1> <3> <4> <4> <4> 00 01, 10, or 11 <1> The TO0n pin output goes high when LVS0n and LVR0n = 10. <2> The TO0n pin output goes low when LVS0n and LVR0n = 01 (the pin output remains unchanged from the high level even if LVS0n and LVR0n are cleared to 00). <3> The timer starts operating when TMC0n3 and TMC0n2 are set to 01, 10, or 11. Because LVS0n and LVR0n were set to 10 before the operation was started, the TO0n pin output starts from the high level. After the timer starts operating, setting LVS0n and LVR0n is prohibited until TMC0n3 and TMC0n2 = 00 (disabling the timer operation). <4> The output level of the TO0n pin is inverted each time an interrupt signal (INTTM00n) is generated. Remark n = 0, 1 User's Manual U17555EJ3V0UD 191 www..com CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Operation As interval timer As square-wave output As external event counter As clear & start mode entered by TI000 pin valid edge input As free-running timer As PPG output As one-shot pulse output As pulse width measurement 0000H CP01n < CR00n FFFFH Setting the same value to CR00n and CP01n is prohibited. Using timer output (TO0n) is prohibited (TOC0n = 00H) Using timer output (TO00) is prohibited when detection of the valid edge of the TI010 pin is used. (TOC00 = 00H) - Restriction - (2) Timer start errors An error of up to one clock may occur in the time required for a match signal to be generated after timer start. This is because counting TM0n is started asynchronously to the count pulse. Figure 6-44. Start Timing of TM0n Count Count pulse TM0n count value 0000H Timer start 0001H 0002H 0003H 0004H (3) Setting of CR00n and CR01n (clear & start mode entered upon a match between TM0n and CR00n) Set a value other than 0000H to CR00n and CR01n (TM0n cannot count one pulse when it is used as an external event counter). Remark n = 0, 1 192 User's Manual U17555EJ3V0UD www..com CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (4) Timing of holding data by capture register (a) When the valid edge is input to the TI000/TI01n pin and the reverse phase of the TI000 pin is detected while CR000/CR01n is read, CR01n performs a capture operation but the read value of CR000/CR01n is not guaranteed. At this time, an interrupt signal (INTTM000/INTTM01n) is generated when the valid edge of the TI000/TI01n pin is detected (the interrupt signal is not generated when the reverse-phase edge of the TI000 pin is detected). When the count value is captured because the valid edge of the TI000/TI01n pin was detected, read the value of CR000/CR01n after INTTM000/INTTM01n is generated. Figure 6-45. Timing of Holding Data by Capture Register Count pulse TM0n count value Edge input INTTM01n Capture read signal Value captured to CR01n X Capture operation N+1 Capture operation is performed but read value is not guaranteed. N N+1 N+2 M M+1 M+2 (b) The values of CR00n and CR01n are not guaranteed after 16-bit timer/event counter 0n stops. (5) Setting valid edge Set the valid edge of the TI000 pin while the timer operation is stopped (TMC003 and TMC002 = 00). Set the valid edge by using ES000 and ES001. (6) Re-triggering one-shot pulse Make sure that the trigger is not generated while an active level is being output in the one-shot pulse output mode. Be sure to input the next trigger after the current active level is output. Remark n = 0, 1 User's Manual U17555EJ3V0UD 193 www..com CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (7) Operation of OVF0n flag (a) Setting OVF0n flag (1) The OVF0n flag is set to 1 in the following case, as well as when TM0n overflows. Select the clear & start mode entered upon a match between TM0n and CR00n. Set CR00n to FFFFH. When TM0n matches CR00n and TM0n is cleared from FFFFH to 0000H Figure 6-46. Operation Timing of OVF0n Flag Count pulse CR00n TM0n OVF0n INTTM00n FFFFH FFFEH FFFFH 0000H 0001H (b) Clearing OVF0n flag Even if the OVF0n flag is cleared to 0 after TM0n overflows and before the next count clock is counted (before the value of TM0n becomes 0001H), it is set to 1 again and clearing is invalid. (8) One-shot pulse output One-shot pulse output operates correctly in the free-running timer mode or the clear & start mode entered by the TI000 pin valid edge. The one-shot pulse cannot be output in the clear & start mode entered upon a match between TM0n and CR00n. Remark n = 0, 1 194 User's Manual U17555EJ3V0UD www..com CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (9) Capture operation (a) When valid edge of TI000 is specified as count clock When the valid edge of TI000 is specified as the count clock, the capture register for which TI000 is specified as a trigger does not operate correctly. (b) Pulse width to accurately capture value by signals input to TI01n and TI000 pins To accurately capture the count value, the pulse input to the TI000 and TI01n pins as a capture trigger must be wider than two count clocks selected by PRM0n (see Figure 6-10). (c) Generation of interrupt signal The capture operation is performed at the falling edge of the count clock but the interrupt signals (INTTM00n and INTTM01n) are generated at the rising edge of the next count clock (see Figure 6-10). (d) Note when CRC001 (bit 1 of capture/compare control register 00 (CRC00)) is set to 1 When the count value of the TM00 register is captured to the CR000 register in the phase reverse to the signal input to the TI000 pin, the interrupt signal (INTTM000) is not generated after the count value is captured. If the valid edge is detected on the TI010 pin during this operation, the capture operation is not performed but the INTTM000 signal is generated as an external interrupt signal. Mask the INTTM000 signal when the external interrupt is not used. (10) Edge detection (a) Specifying valid edge after reset If the operation of the 16-bit timer/event counter 0n is enabled after reset and while the TI000 or TI01n pin is at high level and when the rising edge or both the edges are specified as the valid edge of the TI000 or TI01n pin, then the high level of the TI000 or TI01n pin is detected as the rising edge. Note this when the TI000 or TI01n pin is pulled up. However, the rising edge is not detected when the operation is once stopped and then enabled again. (b) Sampling clock for eliminating noise The sampling clock for eliminating noise differs depending on whether the valid edge of TI000 is used as the count clock or capture trigger. In the former case, the sampling clock is fixed to fPRS. In the latter, the count clock selected by PRM00 is used for sampling. When the signal input to the TI000 pin is sampled and the valid level is detected two times in a row, the valid edge is detected. Therefore, noise having a short pulse width can be eliminated (see Figure 6-10). (11) Timer operation The signal input to the TI000/TI01n pin is not acknowledged while the timer is stopped, regardless of the operation mode of the CPU. Remarks 1. fPRS: Peripheral hardware clock frequency 2. n = 0, 1 User's Manual U17555EJ3V0UD 195 www..com CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 7.1 Functions of 8-Bit Timer/Event Counters 50 and 51 8-bit timer/event counters 50 and 51 have the following functions. * Interval timer * External event counter * Square-wave output * PWM output Figures 7-1 and 7-2 show the block diagrams of 8-bit timer/event counters 50 and 51. Figure 7-1. Block Diagram of 8-Bit Timer/Event Counter 50 Internal bus Mask circuit TI50/TO50/ P17 fPRS fPRS/2 fPRS/22 fPRS/26 fPRS/28 fPRS/213 8-bit timer compare register 50 (CR50) Match Selector Selector Note 1 INTTM50 To TMH0 To UART0 To UART6 TO50/TI50/ P17 Output latch (P17) PM17 8-bit timer OVF counter 50 (TM50) Clear R Note 2 S R Invert level 3 Selector TCL502 TCL501 TCL500 Timer clock selection register 50 (TCL50) TCE50 TMC506 LVS50 LVR50 TMC501 TOE50 8-bit timer mode control register 50 (TMC50) Internal bus Notes 1. 2. Timer output F/F PWM output F/F 196 User's Manual U17555EJ3V0UD Selector S Q INV www..com CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 7-2. Block Diagram of 8-Bit Timer/Event Counter 51 Internal bus Mask circuit 8-bit timer compare register 51 (CR51) TI51/TO51/P33/INTP4 fPRS fPRS/2 fPRS/24 fPRS/26 fPRS/28 fPRS/212 Match Selector Note 1 INTTM51 Selector 8-bit timer OVF counter 51 (TM51) Clear Selector S Q INV R Note 2 S R Invert level TO51/TI51/ P33/INTP4 Output latch (P33) PM33 3 Selector TCL512 TCL511 TCL510 Timer clock selection register 51 (TCL51) TCE51 TMC516 LVS51 LVR51 TMC511 TOE51 8-bit timer mode control register 51 (TMC51) Internal bus Notes 1. 2. Timer output F/F PWM output F/F User's Manual U17555EJ3V0UD 197 www..com CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 7.2 Configuration of 8-Bit Timer/Event Counters 50 and 51 8-bit timer/event counters 50 and 51 include the following hardware. Table 7-1. Configuration of 8-Bit Timer/Event Counters 50 and 51 Item Timer register Register Timer input Timer output Control registers 8-bit timer counter 5n (TM5n) 8-bit timer compare register 5n (CR5n) TI5n TO5n Timer clock selection register 5n (TCL5n) 8-bit timer mode control register 5n (TMC5n) Port mode register 1 (PM1) or port mode register 3 (PM3) Port register 1 (P1) or port register 3 (P3) Configuration (1) 8-bit timer counter 5n (TM5n) TM5n is an 8-bit register that counts the count pulses and is read-only. The counter is incremented in synchronization with the rising edge of the count clock. Figure 7-3. Format of 8-Bit Timer Counter 5n (TM5n) Address: FF16H (TM50), FF1FH (TM51) Symbol TM5n (n = 0, 1) After reset: 00H R In the following situations, the count value is cleared to 00H. <1> Reset signal generation <2> When TCE5n is cleared <3> When TM5n and CR5n match in the mode in which clear & start occurs upon a match of the TM5n and CR5n. Remark n = 0, 1 198 User's Manual U17555EJ3V0UD www..com CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 (2) 8-bit timer compare register 5n (CR5n) CR5n can be read and written by an 8-bit memory manipulation instruction. Except in PWM mode, the value set in CR5n is constantly compared with the 8-bit timer counter 5n (TM5n) count value, and an interrupt request (INTTM5n) is generated if they match. In PWM mode, when the TO5n pin becomes active due to a TM5n overflow and the values of TM5n and CR5n match, the TO5n pin becomes inactive. The value of CR5n can be set within 00H to FFH. Reset signal generation clears CR5n to 00H. Figure 7-4. Format of 8-Bit Timer Compare Register 5n (CR5n) Address: FF17H (CR50), FF41H (CR51) Symbol CR5n (n = 0, 1) After reset: 00H R/W Cautions 1. In the mode in which clear & start occurs on a match of TM5n and CR5n (TMC5n6 = 0), do not write other values to CR5n during operation. 2. In PWM mode, make the CR5n rewrite period 3 count clocks of the count clock (clock selected by TCL5n) or more. Remark n = 0, 1 User's Manual U17555EJ3V0UD 199 www..com CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 7.3 Registers Controlling 8-Bit Timer/Event Counters 50 and 51 The following four registers are used to control 8-bit timer/event counters 50 and 51. * Timer clock selection register 5n (TCL5n) * 8-bit timer mode control register 5n (TMC5n) * Port mode register 1 (PM1) or port mode register 3 (PM3) * Port register 1 (P1) or port register 3 (P3) (1) Timer clock selection register 5n (TCL5n) This register sets the count clock of 8-bit timer/event counter 5n and the valid edge of the TI5n pin input. TCL5n can be set by an 8-bit memory manipulation instruction. Reset signal generation clears TCL5n to 00H. Remark n = 0, 1 Figure 7-5. Format of Timer Clock Selection Register 50 (TCL50) Address: FF6AH Symbol TCL50 7 0 After reset: 00H 6 0 R/W 5 0 4 0 3 0 2 TCL502 1 TCL501 0 TCL500 TCL502 TCL501 TCL500 Count clock selection fPRS = 4 MHz Note 1 fPRS = 8 MHz fPRS = 10 MHz fPRS = 20 MHz 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 TI50 pin falling edge TI50 pin rising edge fPRS fPRS/2 fPRS/2 fPRS/2 fPRS/2 fPRS/2 2 Note 2 4 MHz 2 MHz 1 MHz 62.5 kHz 15.62 kHz 0.48 kHz 8 MHz 4 MHz 2 MHz 125 kHz 31.25 kHz 0.97 kHz 10 MHz 5 MHz 2.5 MHz 20 MHz 10 MHz 5 MHz 6 156.25 kHz 312.5 kHz 39.06 kHz 1.22 kHz 78.13 kHz 2.44 kHz 8 13 Notes 1. 2. In the on-board mode, the FLMD0 pin falling edge is selected. In the on-board mode, the FLMD0 pin rising edge is selected. Cautions 1. When rewriting TCL50 to other data, stop the timer operation beforehand. 2. Be sure to set bits 3 to 7 to 0. Remark fPRS: Peripheral hardware clock frequency 200 User's Manual U17555EJ3V0UD www..com CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 7-6. Format of Timer Clock Selection Register 51 (TCL51) Address: FF8CH Symbol TCL51 7 0 After reset: 00H 6 0 R/W 5 0 4 0 3 0 2 TCL512 1 TCL511 0 TCL510 TCL512 TCL511 TCL510 Count clock selection fPRS = 4 MHz fPRS = 8 MHz fPRS = 10 MHz fPRS = 20 MHz 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 TI51 pin falling edge TI51 pin rising edge fPRS fPRS/2 fPRS/2 fPRS/2 fPRS/2 fPRS/2 4 4 MHz 2 MHz 500 kHz 62.5 kHz 15.62 kHz 0.97 kHz 8 MHz 4 MHz 1 MHz 125 kHz 31.25 kHz 1.95 kHz 10 MHz 5 MHz 625 kHz 20 MHz 10 MHz 1.25 MHz 6 156.25 kHz 312.5 kHz 39.06 kHz 2.44 kHz 78.13 kHz 4.88 kHz 8 12 Cautions 1. When rewriting TCL51 to other data, stop the timer operation beforehand. 2. Be sure to set bits 3 to 7 to 0. Remark fPRS: Peripheral hardware clock frequency User's Manual U17555EJ3V0UD 201 www..com CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 (2) 8-bit timer mode control register 5n (TMC5n) TMC5n is a register that performs the following five types of settings. <1> 8-bit timer counter 5n (TM5n) count operation control <2> 8-bit timer counter 5n (TM5n) operating mode selection <3> Timer output F/F (flip flop) status setting <4> Active level selection in timer F/F control or PWM (free-running) mode. <5> Timer output control TMC5n can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Remark n = 0, 1 Figure 7-7. Format of 8-Bit Timer Mode Control Register 50 (TMC50) Address: FF6BH Symbol TMC50 After reset: 00H <7> TCE50 6 TMC506 R/W Note 5 0 4 0 <3> LVS50 <2> LVR50 1 TMC501 <0> TOE50 TCE50 0 1 TM50 count operation control After clearing to 0, count operation disabled (counter stopped) Count operation start TMC506 0 1 TM50 operating mode selection Mode in which clear & start occurs on a match between TM50 and CR50 PWM (free-running) mode LVS50 0 0 1 1 LVR50 0 1 0 1 No change Timer output F/F status setting Timer output F/F reset (0) Timer output F/F set (1) Setting prohibited TMC501 In other modes (TMC506 = 0) Timer F/F control In PWM mode (TMC506 = 1) Active level selection Active-high Active-low 0 1 Inversion operation disabled Inversion operation enabled TOE50 0 1 Timer output control Output disabled (TM50 output is low level) Output enabled Note Bits 2 and 3 are write-only. (Refer to Cautions and Remarks on the next page.) 202 User's Manual U17555EJ3V0UD www..com CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 7-8. Format of 8-Bit Timer Mode Control Register 51 (TMC51) Address: FF43H Symbol TMC51 After reset: 00H <7> TCE51 6 TMC516 R/W Note 5 0 4 0 <3> LVS51 <2> LVR51 1 TMC511 <0> TOE51 TCE51 0 1 TM51 count operation control After clearing to 0, count operation disabled (counter stopped) Count operation start TMC516 0 1 TM51 operating mode selection Mode in which clear & start occurs on a match between TM51 and CR51 PWM (free-running) mode LVS51 0 0 1 1 LVR51 0 1 0 1 No change Timer output F/F status setting Timer output F/F reset (0) Timer output F/F set (1) Setting prohibited TMC511 In other modes (TMC516 = 0) Timer F/F control In PWM mode (TMC516 = 1) Active level selection Active-high Active-low 0 1 Inversion operation disabled Inversion operation enabled TOE51 0 1 Timer output control Output disabled (TM51 output is low level) Output enabled Note Bits 2 and 3 are write-only. Cautions 1. The settings of LVS5n and LVR5n are valid in other than PWM mode. 2. Perform <1> to <4> below in the following order, not at the same time. <1> Set TMC5n1, TMC5n6: <2> Set TOE5n to enable output: <4> Set TCE5n 3. Stop operation before rewriting TMC5n6. Remarks 1. In PWM mode, PWM output is made inactive by clearing TCE5n to 0. 2. If LVS5n and LVR5n are read, the value is 0. 3. The values of the TMC5n6, LVS5n, LVR5n, TMC5n1, and TOE5n bits are reflected at the TO5n pin regardless of the value of TCE5n. 4. n = 0, 1 Operation mode setting Timer output enable <3> Set LVS5n, LVR5n (see Caution 1): Timer F/F setting User's Manual U17555EJ3V0UD 203 www..com CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 (3) Port mode registers 1 and 3 (PM1, PM3) These registers set port 1 and 3 input/output in 1-bit units. When using the P17/TO50/TI50 and P33/TO51/TI51/INTP4 pins for timer output, clear PM17 and PM33 and the output latches of P17 and P33 to 0. When using the P17/TO50/TI50 and P33/TO51/TI51/INTP4 pins for timer input, set PM17 and PM33 to 1. The output latches of P17 and P33 at this time may be 0 or 1. PM1 and PM3 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets these registers to FFH. Figure 7-9. Format of Port Mode Register 1 (PM1) Address: FF21H Symbol PM1 7 PM17 After reset: FFH 6 PM16 R/W 5 PM15 4 PM14 3 PM13 2 PM12 1 PM11 0 PM10 PM1n 0 1 P1n pin I/O mode selection (n = 0 to 7) Output mode (output buffer on) Input mode (output buffer off) Figure 7-10. Format of Port Mode Register 3 (PM3) Address: FF23H Symbol PM3 7 1 After reset: FFH 6 1 R/W 5 1 4 1 3 PM33 2 PM32 1 PM31 0 PM30 PM3n 0 1 P3n pin I/O mode selection (n = 0 to 3) Output mode (output buffer on) Input mode (output buffer off) 204 User's Manual U17555EJ3V0UD www..com CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 7.4 Operations of 8-Bit Timer/Event Counters 50 and 51 7.4.1 Operation as interval timer 8-bit timer/event counter 5n operates as an interval timer that generates interrupt requests repeatedly at intervals of the count value preset to 8-bit timer compare register 5n (CR5n). When the count value of 8-bit timer counter 5n (TM5n) matches the value set to CR5n, counting continues with the TM5n value cleared to 0 and an interrupt request signal (INTTM5n) is generated. The count clock of TM5n can be selected with bits 0 to 2 (TCL5n0 to TCL5n2) of timer clock selection register 5n (TCL5n). Setting <1> Set the registers. * TCL5n: * CR5n: * TMC5n: Select the count clock. Compare value Stop the count operation, select the mode in which clear & start occurs on a match of TM5n and CR5n. (TMC5n = 0000xxx0B x = Don't care) <2> After TCE5n = 1 is set, the count operation starts. <3> If the values of TM5n and CR5n match, INTTM5n is generated (TM5n is cleared to 00H). <4> INTTM5n is generated repeatedly at the same interval. Set TCE5n to 0 to stop the count operation. Caution Do not write other values to CR5n during operation. Figure 7-11. Interval Timer Operation Timing (1/2) (a) Basic operation t Count clock TM5n count value 00H 01H N 00H 01H N 00H 01H N Count start CR5n TCE5n INTTM5n N Clear N Clear N N Interrupt acknowledged Interval time Interrupt acknowledged Interval time Remark Interval time = (N + 1) x t N = 00H to FFH n = 0, 1 User's Manual U17555EJ3V0UD 205 www..com CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 7-11. Interval Timer Operation Timing (2/2) (b) When CR5n = 00H t Count clock TM5n 00H CR5n TCE5n INTTM5n Interval time 00H 00H 00H 00H (c) When CR5n = FFH t Count clock TM5n CR5n TCE5n INTTM5n Interrupt acknowledged Interval time Interrupt acknowledged FF 01 FE FF FF 00 FE FF FF 00 Remark n = 0, 1 206 User's Manual U17555EJ3V0UD www..com CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 7.4.2 Operation as external event counter The external event counter counts the number of external clock pulses to be input to the TI5n pin by 8-bit timer counter 5n (TM5n). TM5n is incremented each time the valid edge specified by timer clock selection register 5n (TCL5n) is input. Either the rising or falling edge can be selected. When the TM5n count value matches the value of 8-bit timer compare register 5n (CR5n), TM5n is cleared to 0 and an interrupt request signal (INTTM5n) is generated. Whenever the TM5n value matches the value of CR5n, INTTM5n is generated. Setting <1> Set each register. * Set the port mode register (PM17 or PM33)Note to 1. * TCL5n: Select TI5n pin input edge. TI5n pin falling edge TCL5n = 00H TI5n pin rising edge TCL5n = 01H * CR5n: Compare value CR5n, disable the timer F/F inversion operation, disable timer output. (TMC5n = 0000xx00B x = Don't care) <2> When TCE5n = 1 is set, the number of pulses input from the TI5n pin is counted. <3> When the values of TM5n and CR5n match, INTTM5n is generated (TM5n is cleared to 00H). <4> After these settings, INTTM5n is generated each time the values of TM5n and CR5n match. Note 8-bit timer/event counter 50: PM17 8-bit timer/event counter 51: PM33 Figure 7-12. External Event Counter Operation Timing (with Rising Edge Specified) TI5n Count start TM5n count value CR5n INTTM5n 00 01 02 03 04 05 N-1 N N 00 01 02 03 * TMC5n: Stop the count operation, select the mode in which clear & start occurs on match of TM5n and Remark N = 00H to FFH n = 0, 1 User's Manual U17555EJ3V0UD 207 www..com CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 7.4.3 Square-wave output operation A square wave with any selected frequency is output at intervals determined by the value preset to 8-bit timer compare register 5n (CR5n). The TO5n pin output status is inverted at intervals determined by the count value preset to CR5n by setting bit 0 (TOE5n) of 8-bit timer mode control register 5n (TMC5n) to 1. This enables a square wave with any selected frequency to be output (duty = 50%). Setting <1> Set each register. * Clear the port output latch (P17 or P33)Note and port mode register (PM17 or PM33)Note to 0. * TCL5n: Select the count clock. * CR5n: Compare value CR5n. LVS5n 1 0 LVR5n 0 1 Timer Output F/F Status Setting High-level output Low-level output * TMC5n: Stop the count operation, select the mode in which clear & start occurs on a match of TM5n and Timer output F/F inversion enabled Timer output enabled (TMC5n = 00001011B or 00000111B) <2> After TCE5n = 1 is set, the count operation starts. <3> The timer output F/F is inverted by a match of TM5n and CR5n. After INTTM5n is generated, TM5n is cleared to 00H. <4> After these settings, the timer output F/F is inverted at the same interval and a square wave is output from TO5n. The frequency is as follows. Frequency = 1/2t (N + 1) (N: 00H to FFH) Note 8-bit timer/event counter 50: P17, PM17 8-bit timer/event counter 51: P33, PM33 Caution Do not write other values to CR5n during operation. Remark n = 0, 1 208 User's Manual U17555EJ3V0UD www..com CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 7-13. Square-Wave Output Operation Timing t Count clock TM5n count value 00H 01H 02H N-1 N 00H 01H 02H N-1 N 00H Count start CR5n N TO5nNote Note The initial value of TO5n output can be set by bits 2 and 3 (LVR5n, LVS5n) of 8-bit timer mode control register 5n (TMC5n). 7.4.4 PWM output operation 8-bit timer/event counter 5n operates as a PWM output when bit 6 (TMC5n6) of 8-bit timer mode control register 5n (TMC5n) is set to 1. The duty pulse determined by the value set to 8-bit timer compare register 5n (CR5n) is output from TO5n. Set the active level width of the PWM pulse to CR5n; the active level can be selected with bit 1 (TMC5n1) of TMC5n. The count clock can be selected with bits 0 to 2 (TCL5n0 to TCL5n2) of timer clock selection register 5n (TCL5n). PWM output can be enabled/disabled with bit 0 (TOE5n) of TMC5n. Caution In PWM mode, make the CR5n rewrite period 3 count clocks of the count clock (clock selected by TCL5n) or more. Remark n = 0, 1 User's Manual U17555EJ3V0UD 209 www..com CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 (1) PWM output basic operation Setting <1> Set each register. * Clear the port output latch (P17 or P33)Note and port mode register (PM17 or PM33)Note to 0. * TCL5n: Select the count clock. * CR5n: Compare value The timer output F/F is not changed. TMC5n1 0 1 Active-high Active-low Active Level Selection * TMC5n: Stop the count operation, select PWM mode. Timer output enabled (TMC5n = 01000001B or 01000011B) <2> The count operation starts when TCE5n = 1. Clear TCE5n to 0 to stop the count operation. Note 8-bit timer/event counter 50: P17, PM17 8-bit timer/event counter 51: P33, PM33 PWM output operation <1> PWM output (output from TO5n) outputs an inactive level until an overflow occurs. <2> When an overflow occurs, the active level is output. The active level is output until CR5n matches the count value of 8-bit timer counter 5n (TM5n). <3> After the CR5n matches the count value, the inactive level is output until an overflow occurs again. <4> Operations <2> and <3> are repeated until the count operation stops. <5> When the count operation is stopped with TCE5n = 0, PWM output becomes inactive. For details of timing, see Figures 7-14 and 7-15. The cycle, active-level width, and duty are as follows. * Cycle = 28t * Active-level width = Nt * Duty = N/28 (N = 00H to FFH) Remark n = 0, 1 210 User's Manual U17555EJ3V0UD www..com CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 7-14. PWM Output Operation Timing (a) Basic operation (active level = H) t Count clock TM5n CR5n TCE5n INTTM5n TO5n <1> <5> <2> Active level <3> Inactive level Active level 00H 01H N FFH 00H 01H 02H N N+1 FFH 00H 01H 02H M 00H (b) CR5n = 00H t Count clock TM5n CR5n TCE5n INTTM5n TO5n L Inactive level Inactive level 00H 01H 00H FFH 00H 01H 02H N N+1 N+2 FFH 00H 01H 02H M 00H (c) CR5n = FFH t TM5n CR5n TCE5n INTTM5n TO5n 00H 01H FFH FFH 00H 01H 02H N N+1 N+2 FFH 00H 01H 02H M 00H Inactive level Active level Active level Inactive level Inactive level Remarks 1. <1> to <3> and <5> in Figure 7-14 (a) correspond to <1> to <3> and <5> in PWM output operation in 7. 4. 4 (1) PWM output basic operation. 2. n = 0, 1 User's Manual U17555EJ3V0UD 211 www..com CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 (2) Operation with CR5n changed Figure 7-15. Timing of Operation with CR5n Changed (a) CR5n value is changed from N to M before clock rising edge of FFH Value is transferred to CR5n at overflow immediately after change. t Count clock TM5n CR5n TCE5n INTTM5n TO5n <2> <1> CR5n change (N M) H N N+1 N+2 N FFH 00H 01H 02H M M M+1 M+2 FFH 00H 01H 02H M M+1 M+2 (b) CR5n value is changed from N to M after clock rising edge of FFH Value is transferred to CR5n at second overflow. t Count clock TM5n CR5n TCE5n INTTM5n TO5n <1> CR5n change (N M) <2> H N N+1 N+2 N FFH 00H 01H 02H N N N+1 N+2 FFH 00H 01H 02H M M M+1 M+2 Caution When reading from CR5n between <1> and <2> in Figure 7-15, the value read differs from the actual value (read value: M, actual value of CR5n: N). 212 User's Manual U17555EJ3V0UD www..com CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 7.5 Cautions for 8-Bit Timer/Event Counters 50 and 51 (1) Timer start error An error of up to one clock may occur in the time required for a match signal to be generated after timer start. This is because 8-bit timer counters 50 and 51 (TM50, TM51) are started asynchronously to the count clock. Figure 7-16. 8-Bit Timer Counter 5n Start Timing Count clock TM5n count value 00H Timer start 01H 02H 03H 04H Remark n = 0, 1 User's Manual U17555EJ3V0UD 213 www..com CHAPTER 8 8-BIT TIMERS H0 AND H1 8.1 Functions of 8-Bit Timers H0 and H1 8-bit timers H0 and H1 have the following functions. * Interval timer * PWM output mode * Square-wave output * Carrier generator mode (8-bit timer H1 only) 8.2 Configuration of 8-Bit Timers H0 and H1 8-bit timers H0 and H1 include the following hardware. Table 8-1. Configuration of 8-Bit Timers H0 and H1 Item Timer register Registers 8-bit timer counter Hn 8-bit timer H compare register 0n (CMP0n) 8-bit timer H compare register 1n (CMP1n) Timer output Control registers TOHn 8-bit timer H mode register n (TMHMDn) 8-bit timer H carrier control register 1 (TMCYC1) Port mode register 1 (PM1) Port register 1 (P1) Note Configuration Note 8-bit timer H1 only Remark n = 0, 1 Figures 8-1 and 8-2 show the block diagrams. 214 User's Manual U17555EJ3V0UD www..com Figure 8-1. Block Diagram of 8-Bit Timer H0 Internal bus 8-bit timer H mode register 0 (TMHMD0) TMHE0 CKS02 CKS01 CKS00 TMMD01 TMMD00 TOLEV0 TOEN0 8-bit timer H compare register 10 (CMP10) 8-bit timer H compare register 00 (CMP00) 3 2 Decoder Selector Match User's Manual U17555EJ3V0UD TOH0/P15 CHAPTER 8 8-BIT TIMERS H0 AND H1 Interrupt generator F/F R Output controller Level inversion Output latch (P15) PM15 fPRS fPRS/2 fPRS/22 fPRS/26 fPRS/210 8-bit timer/ event counter 50 output Selector 8-bit timer counter H0 Clear PWM mode signal 1 0 INTTMH0 Timer H enable signal 215 www..com Selector 216 8-bit timer H mode register 1 (TMHMD1) TMHE1 CKS12 CKS11 CKS10 TMMD11 TMMD10 TOLEV1 TOEN1 3 2 Decoder User's Manual U17555EJ3V0UD Figure 8-2. Block Diagram of 8-Bit Timer H1 Internal bus 8-bit timer H carrier control register 1 RMC1 NRZB1 NRZ1 (TMCYC1) Reload/ interrupt control INTTM51 TOH1/ INTP5/ P16 8-bit timer H compare register 1 1 (CMP11) 8-bit timer H compare register 0 1 (CMP01) CHAPTER 8 8-BIT TIMERS H0 AND H1 Selector Match fPRS fPRS/22 fPRS/24 fPRS/26 fPRS/212 fRL fRL/27 fRL/29 Interrupt generator F/F R Output controller Level inversion Output latch (P16) PM16 8-bit timer counter H1 Carrier generator mode signal PWM mode signal 1 0 INTTMH1 Clear Timer H enable signal www..com CHAPTER 8 8-BIT TIMERS H0 AND H1 (1) 8-bit timer H compare register 0n (CMP0n) Address: FF02H (CMP00), FF1AH (CMP01) Symbol CMP0n (n = 0, 1) 7 6 5 4 After reset: 00H 3 R/W 2 1 0 Caution CMP0n cannot be rewritten during timer count operation. CMP0n can be refreshed (the same value is written) during timer count operation. (2) 8-bit timer H compare register 1n (CMP1n) This register can be read or written by an 8-bit memory manipulation instruction. This register is used in the PWM output mode and carrier generator mode. In the PWM output mode, this register constantly compares the value set to CMP1n with the count value of the 8bit timer counter Hn and, when the two values match, inverts the output level of TOHn. No interrupt request signal is generated. In the carrier generator mode, the CMP1n register always compares the value set to CMP1n with the count value of the 8-bit timer counter Hn and, when the two values match, generates an interrupt request signal (INTTMHn). At the same time, the count value is cleared. CMP1n can be refreshed (the same value is written) and rewritten during timer count operation. If the value of CMP1n is rewritten while the timer is operating, the new value is latched and transferred to CMP1n when the count value of the timer matches the old value of CMP1n, and then the value of CMP1n is changed to the new value. If matching of the count value and the CMP1n value and writing a value to CMP1n conflict, the value of CMP1n is not changed. A reset signal generation clears this register to 00H. Figure 8-4. Format of 8-Bit Timer H Compare Register 1n (CMP1n) Address: FF0EH (CMP10), FF1BH (CMP11) Symbol CMP1n (n = 0, 1) 7 6 5 4 After reset: 00H 3 R/W 2 1 0 Caution In the PWM output mode and carrier generator mode, be sure to set CMP1n when starting the timer count operation (TMHEn = 1) after the timer count operation was stopped (TMHEn = 0) (be sure to set again even if setting the same value to CMP1n). Remark n = 0, 1 User's Manual U17555EJ3V0UD 217 www..com CHAPTER 8 8-BIT TIMERS H0 AND H1 8.3 Registers Controlling 8-Bit Timers H0 and H1 The following four registers are used to control 8-bit timers H0 and H1. * 8-bit timer H mode register n (TMHMDn) * 8-bit timer H carrier control register 1 (TMCYC1)Note * Port mode register 1 (PM1) * Port register 1 (P1) Note 8-bit timer H1 only (1) 8-bit timer H mode register n (TMHMDn) This register controls the mode of timer H. This register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Remark n = 0, 1 218 User's Manual U17555EJ3V0UD www..com CHAPTER 8 8-BIT TIMERS H0 AND H1 Figure 8-5. Format of 8-Bit Timer H Mode Register 0 (TMHMD0) Address: FF69H Symbol TMHMD0 <7> TMHE0 After reset: 00H 6 CKS02 R/W 5 CKS01 4 CKS00 3 TMMD01 2 TMMD00 <1> TOLEV0 <0> TOEN0 TMHE0 0 1 Timer operation enable Stops timer count operation (Counter is cleared to 0) Enables timer count operation (Count operation started by inputting clock) CKS02 CKS01 CKS00 Count clock selection fPRS = 4 MHz fPRS = 8 MHz 8 MHz 4 MHz 2 MHz 125 kHz 7.81 kHz fPRS = 10 MHz 10 MHz 5 MHz 2.5 MHz fPRS = 20 MHz 20 MHz 10 MHz 5 MHz 0 0 0 0 1 1 0 0 1 1 0 0 Other than above 0 1 0 1 0 1 fPRS fPRS/2 fPRS/2 fPRS/2 fPRS/2 2 4 MHz 2 MHz 1 MHz 62.5 kHz 3.90 kHz Note 6 156.25 kHz 312.5 kHz 9.77 kHz 19.54 kHz 10 TM50 output Setting prohibited TMMD01 0 1 TMMD00 0 0 Interval timer mode PWM output mode Setting prohibited Timer operation mode Other than above TOLEV0 0 1 Low level High level Timer output level control (in default mode) TOEN0 0 1 Disables output Enables output Timer output control Note When TM50 output as the count clock. * Set to PWM mode (TMC506 = 1) after the following order to bellow. <1>Set the count clock to make the duty = 50%. <2>Start the operation of 8-bit timer/event counter 50. * Set to Mode in which the count clock is cleared and started upon a match of TM50 and CR50 (TMC506 = 0) after the following order to bellow. <1>Enable the timer F/F inversion operation (TMC501 = 1). <2>Start the operation of 8-bit timer/event counter 50. It is not necessary to enable the TO50 pin as a timer output pin in any mode. User's Manual U17555EJ3V0UD 219 www..com CHAPTER 8 8-BIT TIMERS H0 AND H1 Cautions 1. When TMHE0 = 1, setting the other bits of TMHMD0 is prohibited. However, TMHMD0 can be refreshed (the same value is written). 2. In the PWM output mode, be sure to set 8-bit timer H compare register 10 (CMP10) when starting the timer count operation (TMHE0 = 1) after the timer count operation was stopped (TMHE0 = 0) (be sure to set again even if setting the same value to CMP10). Remarks 1. fPRS: Peripheral hardware clock frequency 2. TMC506: Bit 6 of 8-bit timer mode control register 50 (TMC50) TMC501: Bit 1 of TMC50 Figure 8-6. Format of 8-Bit Timer H Mode Register 1 (TMHMD1) Address: FFFAH Symbol TMHMD1 <7> TMHE1 After reset: 00H 6 CKS12 R/W 5 CKS11 4 CKS10 3 TMMD11 2 TMMD10 <1> TOLEV1 <0> TOEN1 TMHE1 0 1 Timer operation enable Stops timer count operation (Counter is cleared to 0) Enables timer count operation (Count operation started by inputting clock) CKS12 CKS11 CKS10 Count clock selection fPRS = 4 MHz fPRS = 8 MHz 8 MHz 2 MHz 1 MHz 125 kHz 1.95 kHz fPRS = 10 MHz 10 MHz 2.5 MHz 625 kHz fPRS = 20 MHz 20 MHz 5 MHz 1.25 MHz 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 fPRS fPRS/2 fPRS/2 fPRS/2 fPRS/2 fRL/2 fRL/2 fRL 7 2 4 MHz 1 MHz 500 kHz 62.5 kHz 0.97 kHz 4 6 156.25 kHz 312.5 kHz 2.44 kHz 4.88 kHz 12 1.88 kHz (TYP.) 0.47 kHz (TYP.) 240 kHz (TYP.) 9 TMMD11 0 TMMD10 0 1 0 1 Interval timer mode Timer operation mode 0 1 1 Carrier generator mode PWM output mode Setting prohibited TOLEV1 0 1 Low level High level Timer output level control (in default mode) TOEN1 0 1 Disables output Enables output Timer output control 220 User's Manual U17555EJ3V0UD www..com CHAPTER 8 8-BIT TIMERS H0 AND H1 Cautions 1. When TMHE1 = 1, setting the other bits of TMHMD1 is prohibited. However, TMHMD1 can be refreshed (the same value is written). 2. In the PWM output mode and carrier generator mode, be sure to set 8-bit timer H compare register 11 (CMP11) when starting the timer count operation (TMHE1 = 1) after the timer count operation was stopped (TMHE1 = 0) (be sure to set again even if setting the same value to CMP11). 3. When the carrier generator mode is used, set so that the count clock frequency of TMH1 becomes more than 6 times the count clock frequency of TM51. Remarks 1. fPRS: Peripheral hardware clock frequency 2. fRL: Internal low-speed oscillation clock frequency (2) 8-bit timer H carrier control register 1 (TMCYC1) This register controls the remote control output and carrier pulse output status of 8-bit timer H1. This register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 8-7. Format of 8-Bit Timer H Carrier Control Register 1 (TMCYC1) Address: FFEEH After reset: 00H R/WNote <0> TMCYC1 0 0 0 0 0 RMC1 NRZB1 NRZ1 RMC1 0 NRZB1 0 1 0 1 Low-level output Remote control output 0 1 1 High-level output at rising edge of INTTM51 signal input Low-level output Carrier pulse output at rising edge of INTTM51 signal input NRZ1 0 1 Carrier pulse output status flag Carrier output disabled status (low-level status) Carrier output enabled status (RMC1 = 1: Carrier pulse output, RMC1 = 0: High-level status) Note Bit 0 is read-only. User's Manual U17555EJ3V0UD 221 www..com CHAPTER 8 8-BIT TIMERS H0 AND H1 (3) Port mode register 1 (PM1) This register sets port 1 input/output in 1-bit units. When using the P15/TOH0 and P16/TOH1/INTP5 pins for timer output, clear PM15 and PM16 and the output latches of P15 and P16 to 0. PM1 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to FFH. Figure 8-8. Format of Port Mode Register 1 (PM1) Address: FF21H Symbol PM1 7 PM17 After reset: FFH 6 PM16 R/W 5 PM15 4 PM14 3 PM13 2 PM12 1 PM11 0 PM10 PM1n 0 1 P1n pin I/O mode selection (n = 0 to 7) Output mode (output buffer on) Input mode (output buffer off) 222 User's Manual U17555EJ3V0UD www..com CHAPTER 8 8-BIT TIMERS H0 AND H1 8.4 Operation of 8-Bit Timers H0 and H1 8.4.1 Operation as interval timer/square-wave output When 8-bit timer counter Hn and compare register 0n (CMP0n) match, an interrupt request signal (INTTMHn) is generated and 8-bit timer counter Hn is cleared to 00H. Compare register 1n (CMP1n) is not used in interval timer mode. Since a match of 8-bit timer counter Hn and the CMP1n register is not detected even if the CMP1n register is set, timer output is not affected. By setting bit 0 (TOENn) of timer H mode register n (TMHMDn) to 1, a square wave of any frequency (duty = 50%) is output from TOHn. (1) Usage Generates the INTTMHn signal repeatedly at the same interval. <1> Set each register. Figure 8-9. Register Setting During Interval Timer/Square-Wave Output Operation (i) Setting timer H mode register n (TMHMDn) TMHEn TMHMDn 0 CKSn2 0/1 CKSn1 0/1 CKSn0 0/1 TMMDn1 TMMDn0 TOLEVn 0 0 0/1 TOENn 0/1 Timer output setting Timer output level inversion setting Interval timer mode setting Count clock (fCNT) selection Count operation stopped (ii) CMP0n register setting * Compare value (N) <2> Count operation starts when TMHEn = 1. <3> When the values of 8-bit timer counter Hn and the CMP0n register match, the INTTMHn signal is generated and 8-bit timer counter Hn is cleared to 00H. Interval time = (N +1)/fCNT <4> Subsequently, the INTTMHn signal is generated at the same interval. To stop the count operation, clear TMHEn to 0. Remark n = 0, 1 User's Manual U17555EJ3V0UD 223 www..com CHAPTER 8 8-BIT TIMERS H0 AND H1 (2) Timing chart The timing of the interval timer/square-wave output operation is shown below. Figure 8-10. Timing of Interval Timer/Square-Wave Output Operation (1/2) (a) Basic operation Count clock Count start 8-bit timer counter Hn 00H 01H N 00H Clear 01H N 00H Clear 01H 00H CMP0n N TMHEn INTTMHn Interval time TOHn <1> <2> Level inversion, match interrupt occurrence, 8-bit timer counter Hn clear <3> <2> Level inversion, match interrupt occurrence, 8-bit timer counter Hn clear <1> The count operation is enabled by setting the TMHEn bit to 1. The count clock starts counting no more than 1 clock after the operation is enabled. <2> When the values of 8-bit timer counter Hn and the CMP0n register match, the value of 8-bit timer counter Hn is cleared, the TOHn output level is inverted, and the INTTMHn signal is output. <3> The INTTMHn signal and TOHn output become inactive by clearing the TMHEn bit to 0 during timer Hn operation. If these are inactive from the first, the level is retained. Remark n = 0, 1 N = 01H to FEH 224 User's Manual U17555EJ3V0UD www..com CHAPTER 8 8-BIT TIMERS H0 AND H1 Figure 8-10. Timing of Interval Timer/Square-Wave Output Operation (2/2) (b) Operation when CMP0n = FFH Count clock Count start 8-bit timer counter Hn 00H 01H FEH FFH 00H Clear FEH FFH 00H Clear CMP0n FFH TMHEn INTTMHn TOHn Interval time (c) Operation when CMP0n = 00H Count clock Count start 8-bit timer counter Hn 00H CMP0n 00H TMHEn INTTMHn TOHn Interval time Remark n = 0, 1 User's Manual U17555EJ3V0UD 225 www..com CHAPTER 8 8-BIT TIMERS H0 AND H1 8.4.2 Operation as PWM output mode In PWM output mode, a pulse with an arbitrary duty and arbitrary cycle can be output. 8-bit timer compare register 0n (CMP0n) controls the cycle of timer output (TOHn). Rewriting the CMP0n register during timer operation is prohibited. 8-bit timer compare register 1n (CMP1n) controls the duty of timer output (TOHn). Rewriting the CMP1n register during timer operation is possible. The operation in PWM output mode is as follows. TOHn output becomes active and 8-bit timer counter Hn is cleared to 0 when 8-bit timer counter Hn and the CMP0n register match after the timer count is started. TOHn output becomes inactive when 8-bit timer counter Hn and the CMP1n register match. (1) Usage In PWM output mode, a pulse for which an arbitrary duty and arbitrary cycle can be set is output. <1> Set each register. Figure 8-11. Register Setting in PWM Output Mode (i) Setting timer H mode register n (TMHMDn) CKSn2 0/1 CKSn1 0/1 CKSn0 0/1 TMMDn1 TMMDn0 TOLEVn 1 0 0/1 TOENn 1 TMHEn TMHMDn 0 Timer output enabled Timer output level inversion setting PWM output mode selection Count clock (fCNT) selection Count operation stopped (ii) Setting CMP0n register * Compare value (N): Cycle setting (iii) Setting CMP1n register * Compare value (M): Duty setting Remarks 1. n = 0, 1 2. 00H CMP1n (M) < CMP0n (N) FFH 226 User's Manual U17555EJ3V0UD www..com CHAPTER 8 8-BIT TIMERS H0 AND H1 <2> The count operation starts when TMHEn = 1. <3> The CMP0n register is the compare register that is to be compared first after counter operation is enabled. When the values of 8-bit timer counter Hn and the CMP0n register match, 8-bit timer counter Hn is cleared, an interrupt request signal (INTTMHn) is generated, and TOHn output becomes active. At the same time, the compare register to be compared with 8-bit timer counter Hn is changed from the CMP0n register to the CMP1n register. <4> When 8-bit timer counter Hn and the CMP1n register match, TOHn output becomes inactive and the compare register to be compared with 8-bit timer counter Hn is changed from the CMP1n register to the CMP0n register. generated. <5> By performing procedures <3> and <4> repeatedly, a pulse with an arbitrary duty can be obtained. <6> To stop the count operation, set TMHEn = 0. If the setting value of the CMP0n register is N, the setting value of the CMP1n register is M, and the count clock frequency is fCNT, the PWM pulse output cycle and duty are as follows. PWM pulse output cycle = (N + 1)/fCNT Duty = Active width : Total width of PWM = (M + 1) : (N + 1) At this time, 8-bit timer counter Hn is not cleared and the INTTMHn signal is not Cautions 1. In PWM output mode, three operation clocks (signal selected using the CKSn2 to CKSn0 bits of the TMHMDn register) are required to transfer the CMP1n register value after rewriting the register. 2. Be sure to set the CMP1n register when starting the timer count operation (TMHEn = 1) after the timer count operation was stopped (TMHEn = 0) (be sure to set again even if setting the same value to the CMP1n register). Remark n = 0, 1 User's Manual U17555EJ3V0UD 227 www..com CHAPTER 8 8-BIT TIMERS H0 AND H1 (2) Timing chart The operation timing in PWM output mode is shown below. Caution Make sure that the CMP1n register setting value (M) and CMP0n register setting value (N) are within the following range. 00H CMP1n (M) < CMP0n (N) FFH Figure 8-12. Operation Timing in PWM Output Mode (1/4) (a) Basic operation Count clock 8-bit timer counter Hn 00H 01H A5H 00H 01H 02H A5H 00H 01H 02H A5H 00H CMP0n A5H CMP1n 01H TMHEn INTTMHn TOHn (TOLEVn = 0) <1> TOHn (TOLEVn = 1) <2> <3> <4> <1> The count operation is enabled by setting the TMHEn bit to 1. Start 8-bit timer counter Hn by masking one count clock to count up. At this time, TOHn output remains inactive (when TOLEVn = 0). <2> When the values of 8-bit timer counter Hn and the CMP0n register match, the TOHn output level is inverted, the value of 8-bit timer counter Hn is cleared, and the INTTMHn signal is output. <3> When the values of 8-bit timer counter Hn and the CMP1n register match, the level of the TOHn output is returned. At this time, the 8-bit timer counter value is not cleared and the INTTMHn signal is not output. <4> Clearing the TMHEn bit to 0 during timer Hn operation makes the INTTMHn signal and TOHn output inactive. Remark n = 0, 1 228 User's Manual U17555EJ3V0UD www..com CHAPTER 8 8-BIT TIMERS H0 AND H1 Figure 8-12. Operation Timing in PWM Output Mode (2/4) (b) Operation when CMP0n = FFH, CMP1n = 00H Count clock 8-bit timer counter Hn 00H 01H FFH 00H 01H 02H FFH 00H 01H 02H FFH 00H CMP0n FFH CMP1n 00H TMHEn INTTMHn TOHn (TOLEVn = 0) (c) Operation when CMP0n = FFH, CMP1n = FEH Count clock 8-bit timer counter Hn 00H 01H FEH FFH 00H 01H FEH FFH 00H 01H FEH FFH 00H CMP0n FFH CMP1n FEH TMHEn INTTMHn TOHn (TOLEVn = 0) Remark n = 0, 1 User's Manual U17555EJ3V0UD 229 www..com CHAPTER 8 8-BIT TIMERS H0 AND H1 Figure 8-12. Operation Timing in PWM Output Mode (3/4) (d) Operation when CMP0n = 01H, CMP1n = 00H Count clock 8-bit timer counter Hn 00H 01H 00H 01H 00H 00H 01H 00H 01H CMP0n 01H CMP1n 00H TMHEn INTTMHn TOHn (TOLEVn = 0) Remark n = 0, 1 230 User's Manual U17555EJ3V0UD www..com CHAPTER 8 8-BIT TIMERS H0 AND H1 Figure 8-12. Operation Timing in PWM Output Mode (4/4) (e) Operation by changing CMP1n (CMP1n = 01H 03H, CMP0n = A5H) Count clock 8-bit timer counter Hn 00H 01H 02H A5H 00H 01H 02H 03H A5H 00H 01H 02H 03H A5H 00H CMP0n A5H CMP1n 01H <2> 01H (03H) <2>' 03H TMHEn INTTMHn TOHn (TOLEVn = 0) <1> <3> <4> <5> <6> <1> The count operation is enabled by setting TMHEn = 1. Start 8-bit timer counter Hn by masking one count clock to count up. At this time, the TOHn output remains inactive (when TOLEVn = 0). <2> The CMP1n register value can be changed during timer counter operation. This operation is asynchronous to the count clock. <3> When the values of 8-bit timer counter Hn and the CMP0n register match, the value of 8-bit timer counter Hn is cleared, the TOHn output becomes active, and the INTTMHn signal is output. <4> If the CMP1n register value is changed, the value is latched and not transferred to the register. When the values of 8-bit timer counter Hn and the CMP1n register before the change match, the value is transferred to the CMP1n register and the CMP1n register value is changed (<2>'). However, three count clocks or more are required from when the CMP1n register value is changed to when the value is transferred to the register. If a match signal is generated within three count clocks, the changed value cannot be transferred to the register. <5> When the values of 8-bit timer counter Hn and the CMP1n register after the change match, the TOHn output becomes inactive. 8-bit timer counter Hn is not cleared and the INTTMHn signal is not generated. <6> Clearing the TMHEn bit to 0 during timer Hn operation makes the INTTMHn signal and TOHn output inactive. Remark n = 0, 1 User's Manual U17555EJ3V0UD 231 www..com CHAPTER 8 8-BIT TIMERS H0 AND H1 8.4.3 Carrier generator mode operation (8-bit timer H1 only) The carrier clock generated by 8-bit timer H1 is output in the cycle set by 8-bit timer/event counter 51. In carrier generator mode, the output of the 8-bit timer H1 carrier pulse is controlled by 8-bit timer/event counter 51, and the carrier pulse is output from the TOH1 output. (1) Carrier generation In carrier generator mode, 8-bit timer H compare register 01 (CMP01) generates a low-level width carrier pulse waveform and 8-bit timer H compare register 11 (CMP11) generates a high-level width carrier pulse waveform. Rewriting the CMP11 register during 8-bit timer H1 operation is possible but rewriting the CMP01 register is prohibited. (2) Carrier output control Carrier output is controlled by the interrupt request signal (INTTM51) of 8-bit timer/event counter 51 and the NRZB1 and RMC1 bits of the 8-bit timer H carrier control register (TMCYC1). The relationship between the outputs is shown below. RMC1 Bit 0 0 1 1 NRZB1 Bit 0 1 0 1 Output Low-level output High-level output Low-level output Carrier pulse output 232 User's Manual U17555EJ3V0UD www..com CHAPTER 8 8-BIT TIMERS H0 AND H1 To control the carrier pulse output during a count operation, the NRZ1 and NRZB1 bits of the TMCYC1 register have a master and slave bit configuration. The NRZ1 bit is read-only but the NRZB1 bit can be read and written. The INTTM51 signal is synchronized with the 8-bit timer H1 count clock and output as the INTTM5H1 signal. The INTTM5H1 signal becomes the data transfer signal of the NRZ1 bit, and the NRZB1 bit value is transferred to the NRZ1 bit. The timing for transfer from the NRZB1 bit to the NRZ1 bit is as shown below. Figure 8-13. Transfer Timing TMHE1 8-bit timer H1 count clock INTTM51 INTTM5H1 <1> NRZ1 0 <2> NRZB1 1 0 1 1 0 RMC1 <1> <2> The INTTM51 signal is synchronized with the count clock of 8-bit timer H1 and is output as the INTTM5H1 signal. The value of the NRZB1 bit is transferred to the NRZ1 bit at the second clock from the rising edge of the INTTM5H1 signal. Cautions 1. Do not rewrite the NRZB1 bit again until at least the second clock after it has been rewritten, or else the transfer from the NRZB1 bit to the NRZ1 bit is not guaranteed. 2. When 8-bit timer/event counter 51 is used in the carrier generator mode, an interrupt is generated at the timing of <1>. When 8-bit timer/event counter 51 is used in a mode other than the carrier generator mode, the timing of the interrupt generation differs. User's Manual U17555EJ3V0UD 233 www..com CHAPTER 8 8-BIT TIMERS H0 AND H1 (3) Usage Outputs an arbitrary carrier clock from the TOH1 pin. <1> Set each register. Figure 8-14. Register Setting in Carrier Generator Mode (i) Setting 8-bit timer H mode register 1 (TMHMD1) CKS12 0/1 CKS11 0/1 CKS10 0/1 TMMD11 TMMD10 TOLEV1 0 1 0/1 TOEN1 1 TMHE1 TMHMD1 0 Timer output enabled Timer output level inversion setting Carrier generator mode selection Count clock (fCNT) selection Count operation stopped (ii) CMP01 register setting * Compare value (iii) CMP11 register setting * Compare value (iv) TMCYC1 register setting * RMC1 = 1 ... Remote control output enable bit * NRZB1 = 0/1 ... carrier output enable bit (v) TCL51 and TMC51 register setting * See 7.3 Registers Controlling 8-Bit Timer/Event Counters 50 and 51. <2> When TMHE1 = 1, 8-bit timer H1 starts counting. <3> When TCE51 of 8-bit timer mode control register 51 (TMC51) is set to 1, 8-bit timer/event counter 51 starts counting. <4> After the count operation is enabled, the first compare register to be compared is the CMP01 register. When the count value of 8-bit timer counter H1 and the CMP01 register value match, the INTTMH1 signal is generated, 8-bit timer counter H1 is cleared, and at the same time, the compare register to be compared with 8-bit timer counter H1 is switched from the CMP01 register to the CMP11 register. <5> When the count value of 8-bit timer counter H1 and the CMP11 register value match, the INTTMH1 signal is generated, 8-bit timer counter H1 is cleared, and at the same time, the compare register to be compared with 8-bit timer counter H1 is switched from the CMP11 register to the CMP01 register. <6> By performing procedures <4> and <5> repeatedly, a carrier clock is generated. <7> The INTTM51 signal is synchronized with count clock of 8-bit timer H1 and output as the INTTM5H1 signal. The INTTM5H1 signal becomes the data transfer signal for the NRZB1 bit, and the NRZB1 bit value is transferred to the NRZ1 bit. <8> When the NRZ1 bit is high level, a carrier clock is output from the TOH1 pin. <9> By performing the procedures above, an arbitrary carrier clock is obtained. To stop the count operation, clear TMHE1 to 0. 234 User's Manual U17555EJ3V0UD www..com CHAPTER 8 8-BIT TIMERS H0 AND H1 If the setting value of the CMP01 register is N, the setting value of the CMP11 register is M, and the count clock frequency is fCNT, the carrier clock output cycle and duty are as follows. Carrier clock output cycle = (N + M + 2)/fCNT Duty = High-level width : Carrier clock output width = ( M + 1) : (N + M + 2) Cautions 1. Be sure to set the CMP11 register when starting the timer count operation (TMHE1 = 1) after the timer count operation was stopped (TMHE1 = 0) (be sure to set again even if setting the same value to the CMP11 register). 2. Set so that the count clock frequency of TMH1 becomes more than 6 times the count clock frequency of TM51. (4) Timing chart The carrier output control timing is shown below. Cautions 1. Set the values of the CMP01 and CMP11 registers in a range of 01H to FFH. 2. In the carrier generator mode, three operating clocks (signal selected by CKS12 to CKS10 bits of TMHMD1 register) or more are required from when the CMP11 register value is changed to when the value is transferred to the register. 3. Be sure to set the RMC1 bit before the count operation is started. User's Manual U17555EJ3V0UD 235 www..com CHAPTER 8 8-BIT TIMERS H0 AND H1 Figure 8-15. Carrier Generator Mode Operation Timing (1/3) (a) Operation when CMP01 = N, CMP11 = N 8-bit timer Hn count clock 8-bit timer counter Hn count value CMPn0 CMPn1 TMHEn INTTMHn <1> <2> Carrier clock 8-bit timer 5n count clock TM5n count value CR5n TCE5n <5> INTTM5n INTTM5Hn NRZBn NRZn Carrier clock TOHn <7> 0 0 1 1 0 1 0 1 0 0 00H 01H L 00H 01H L 00H 01H L L 00H 01H L 00H 01H 00H N 00H N 00H N 00H N N 00H N 00H N N <3> <4> <6> <1> When TMHE1 = 0 and TCE51 = 0, 8-bit timer counter H1 operation is stopped. <2> When TMHE1 = 1 is set, 8-bit timer counter H1 starts a count operation. At that time, the carrier clock is held at the inactive level. <3> When the count value of 8-bit timer counter H1 matches the CMP01 register value, the first INTTMH1 signal is generated, the carrier clock signal is inverted, and the compare register to be compared with 8-bit timer counter H1 is switched from the CMP01 register to the CMP11 register. 8-bit timer counter H1 is cleared to 00H. <4> When the count value of 8-bit timer counter H1 matches the CMP11 register value, the INTTMH1 signal is generated, the carrier clock signal is inverted, and the compare register to be compared with 8-bit timer counter H1 is switched from the CMP11 register to the CMP01 register. 8-bit timer counter H1 is cleared to 00H. By performing procedures <3> and <4> repeatedly, a carrier clock with duty fixed to 50% is generated. <5> When the INTTM51 signal is generated, it is synchronized with 8-bit timer H1 count clock and output as the INTTM5H1 signal. <6> The INTTM5H1 signal becomes the data transfer signal for the NRZB1 bit, and the NRZB1 bit value is transferred to the NRZ1 bit. <7> When NRZ1 = 0 is set, the TOH1 output becomes low level. 236 User's Manual U17555EJ3V0UD www..com CHAPTER 8 8-BIT TIMERS H0 AND H1 Figure 8-15. Carrier Generator Mode Operation Timing (2/3) (b) Operation when CMP01 = N, CMP11 = M 8-bit timer Hn count clock 8-bit timer counter Hn count value CMPn0 CMPn1 TMHEn INTTMHn <1> <2> Carrier clock 8-bit timer 5n count clock TM5n count value CR5n TCE5n <5> INTTM5n INTTM5Hn NRZBn NRZn Carrier clock <6> TOHn <7> 0 0 1 1 0 0 1 1 0 0 00H 01H L 00H 01H L 00H 01H L L 00H 01H L 00H 01H 00H N 00H 01H M 00H N N 00H 01H M 00H N 00H M <3> <4> <1> When TMHE1 = 0 and TCE51 = 0, 8-bit timer counter H1 operation is stopped. <2> When TMHE1 = 1 is set, 8-bit timer counter H1 starts a count operation. At that time, the carrier clock is held at the inactive level. <3> When the count value of 8-bit timer counter H1 matches the CMP01 register value, the first INTTMH1 signal is generated, the carrier clock signal is inverted, and the compare register to be compared with 8-bit timer counter H1 is switched from the CMP01 register to the CMP11 register. 8-bit timer counter H1 is cleared to 00H. <4> When the count value of 8-bit timer counter H1 matches the CMP11 register value, the INTTMH1 signal is generated, the carrier clock signal is inverted, and the compare register to be compared with 8-bit timer counter H1 is switched from the CMP11 register to the CMP01 register. 8-bit timer counter H1 is cleared to 00H. By performing procedures <3> and <4> repeatedly, a carrier clock with duty fixed to other than 50% is generated. <5> When the INTTM51 signal is generated, it is synchronized with 8-bit timer H1 count clock and output as the INTTM5H1 signal. <6> A carrier signal is output at the first rising edge of the carrier clock if NRZ1 is set to 1. <7> When NRZ1 = 0, the TOH1 output is held at the high level and is not changed to low level while the carrier clock is high level (from <6> and <7>, the high-level width of the carrier clock waveform is guaranteed). User's Manual U17555EJ3V0UD 237 www..com CHAPTER 8 8-BIT TIMERS H0 AND H1 Figure 8-15. Carrier Generator Mode Operation Timing (3/3) (c) Operation when CMP11 is changed 8-bit timer H1 count clock 8-bit timer counter H1 count value 00H 01H N 00H 01H M 00H N 00H 01H L 00H CMP01 <3> CMP11 M M (L) N <3>' L TMHE1 INTTMH1 <2> Carrier clock <1> <4> <5> <1> When TMHE1 = 1 is set, 8-bit timer H1 starts a count operation. At that time, the carrier clock is held at the inactive level. <2> When the count value of 8-bit timer counter H1 matches the CMP01 register value, 8-bit timer counter H1 is cleared and the INTTMH1 signal is output. <3> The CMP11 register can be rewritten during 8-bit timer H1 operation, however, the changed value (L) is latched. The CMP11 register is changed when the count value of 8-bit timer counter H1 and the CMP11 register value before the change (M) match (<3>'). <4> When the count value of 8-bit timer counter H1 and the CMP11 register value before the change (M) match, the INTTMH1 signal is output, the carrier signal is inverted, and 8-bit timer counter H1 is cleared to 00H. <5> The timing at which the count value of 8-bit timer counter H1 and the CMP11 register value match again is indicated by the value after the change (L). 238 User's Manual U17555EJ3V0UD www..com CHAPTER 9 WATCH TIMER 9.1 Functions of Watch Timer The watch timer has the following functions. * Watch timer * Interval timer The watch timer and the interval timer can be used simultaneously. Figure 9-1 shows the watch timer block diagram. Figure 9-1. Block Diagram of Watch Timer Selector Clear fWX 5-bit counter Clear fWX/25 Selector fWX/24 INTWT Selector fPRS/2 7 fW 11-bit prescaler fW/24 fW/25 fW/26 fW/27 fW/28 fW/210 fW/211 fW/29 fSUB Selector INTWTI WTM7 WTM6 WTM5 WTM4 WTM3 WTM2 WTM1 WTM0 Watch timer operation mode register (WTM) Internal bus Remark fPRS: Peripheral hardware clock frequency fSUB: Subsystem clock frequency fW: Watch timer clock frequency (fPRS/27 or fSUB) fWX: fW or fW/29 User's Manual U17555EJ3V0UD 239 www..com CHAPTER 9 WATCH TIMER (1) Watch timer When the high-speed system clock or subsystem clock is used, interrupt requests (INTWT) are generated at preset intervals. Table 9-1. Watch Timer Interrupt Time Interrupt Time 4 When Operated at fSUB = 32.768 kHz 488 s 977 s 0.25 s 0.5 s When Operated at fPRS = 4 MHz 0.51 ms 1.03 ms 0.26 s 0.53 s When Operated at fPRS = 5 MHz 410 s 819 s 0.210 s 0.419 s When Operated at fPRS = 10 MHz 205 s 410 s 0.105 s 0.210 s When Operated at fPRS = 20 MHz 102 s 205 s 520 s 0.105 s 2 /fW 2 /fW 2 /fW 2 /fW 14 13 5 Remark fPRS: Peripheral hardware clock frequency fSUB: Subsystem clock frequency fW: Watch timer clock frequency (fPRS/27 or fSUB) (2) Interval timer Interrupt requests (INTWTI) are generated at preset time intervals. Table 9-2. Interval Timer Interval Time Interrupt Time 4 When Operated at fSUB = 32.768 kHz 488 s 977 s 1.95 ms 3.91 ms 7.81 ms 15.6 ms 31.3 ms 62.5 ms When Operated at fPRS = 4 MHz 0.51 ms 1.03 ms 2.05 ms 4.1 ms 8.2 ms 16.4 ms 32.75 ms 65.55 ms When Operated at fPRS = 5 MHz 410 s 820 s 1.64 ms 3.28 ms 6.55 ms 13.1 ms 26.2 ms 52.4 ms When Operated at fPRS = 10 MHz 205 s 410 s 820 s 1.64 ms 3.28 ms 6.55 ms 13.1 ms 26.2 ms When Operated at fPRS = 20 MHz 102 s 205 s 410 s 820 s 1.64 ms 3.28 ms 6.55 ms 13.1 ms 2 /fW 2 /fW 2 /fW 2 /fW 2 /fW 2 /fW 2 /fW 2 /fW 11 10 9 8 7 6 5 Remark fPRS: Peripheral hardware clock frequency fSUB: Subsystem clock frequency fW: Watch timer clock frequency (fPRS/27 or fSUB) 9.2 Configuration of Watch Timer The watch timer includes the following hardware. Table 9-3. Watch Timer Configuration Item Counter Prescaler Control register 5 bits x 1 11 bits x 1 Watch timer operation mode register (WTM) Configuration 240 User's Manual U17555EJ3V0UD www..com CHAPTER 9 WATCH TIMER 9.3 Register Controlling Watch Timer The watch timer is controlled by the watch timer operation mode register (WTM). * Watch timer operation mode register (WTM) This register sets the watch timer count clock, enables/disables operation, prescaler interval time, and 5-bit counter operation control. WTM is set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears WTM to 00H. Figure 9-2. Format of Watch Timer Operation Mode Register (WTM) Address: FF8FH Symbol WTM 7 WTM7 After reset: 00H 6 WTM6 R/W 5 WTM5 4 WTM4 3 WTM3 2 WTM2 <1> WTM1 <0> WTM0 WTM7 fSUB = 32.768 kHz 0 1 fPRS/2 fSUB 7 Watch timer count clock selection (fW) fPRS = 4 MHz 31.25 kHz fPRS = 8 MHz 62.5 kHz - fPRS = 10 MHz 78.125 kHz fPRS = 20 MHz 156.25 kHz - 32.768 kHz WTM6 0 0 0 0 1 1 1 1 WTM5 0 0 1 1 0 0 1 1 WTM4 0 1 0 1 0 1 0 1 2 /fW 2 /fW 2 /fW 2 /fW 2 /fW 2 /fW 2 /fW 2 /fW 11 10 9 8 7 6 5 4 Prescaler interval time selection WTM3 0 0 1 1 WTM2 0 1 0 1 2 /fW 2 /fW 2 /fW 2 /fW 4 5 13 14 Interrupt time selection WTM1 0 1 Clear after operation stop Start 5-bit counter operation control WTM0 Watch timer operation enable Operation stop (clear both prescaler and 5-bit counter) Operation enable 0 1 User's Manual U17555EJ3V0UD 241 www..com CHAPTER 9 WATCH TIMER Caution Do not change the count clock and interval time (by setting bits 4 to 7 (WTM4 to WTM7) of WTM) during watch timer operation. Remarks 1. fW: Watch timer clock frequency (fPRS/27 or fSUB) 2. fPRS: Peripheral hardware clock frequency 3. fSUB: Subsystem clock frequency 242 User's Manual U17555EJ3V0UD www..com CHAPTER 9 WATCH TIMER 9.4 Watch Timer Operations 9.4.1 Watch timer operation WTM3 WTM2 Interrupt Time When Operated at When Operated at When Operated at When Operated at When Operated at Selection 14 fSUB = 32.768 kHz (WTM7 = 1) fPRS = 4 MHz (WTM7 = 0) 0.53 s 0.26 s 1.03 ms 0.51 ms 7 fPRS = 5 MHz (WTM7 = 0) 0.419 s 0.210 s 819 s 410 s fPRS = 10 MHz (WTM7 = 0) 0.210 s 0.105 s 410 s 205 s fPRS = 20 MHz (WTM7 = 0) 0.105 s 52.5 ms 205 s 102 s 0 0 1 0 1 2 /fW 2 /fW 2 /fW 2 /fW 4 5 13 0.5 s 0.25 s 977 s 488 s 0 1 1 Remarks 1. fW: Watch timer clock frequency (fPRS/2 or fSUB) 2. fPRS: Peripheral hardware clock frequency 3. fSUB: Subsystem clock frequency User's Manual U17555EJ3V0UD 243 www..com CHAPTER 9 WATCH TIMER 9.4.2 Interval timer operation The watch timer operates as interval timer which generates interrupt requests (INTWTI) repeatedly at an interval of the preset count value. The interval time can be selected with bits 4 to 6 (WTM4 to WTM6) of the watch timer operation mode register (WTM). When bit 0 (WTM0) of the WTM is set to 1, the count operation starts. When this bit is set to 0, the count operation stops. Table 9-5. Interval Timer Interval Time WTM6 WTM5 WTM4 Interval Time When Operated When Operated When Operated When Operated When Operated at fSUB = 32.768 kHz (WTM7 = 1) 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 2 /fW 2 /fW 2 /fW 2 /fW 2 /fW 2 /fW 2 /fW 2 /fW 11 10 9 8 7 6 5 4 at fPRS = 4 MHz (WTM7 = 0) 0.51 ms 1.03 ms 2.05 ms 4.1 ms 8.2 ms 16.4 ms 32.75 ms 65.55 ms 7 at fPRS = 5 MHz at fPRS = 10 MHz at fPRS = 20 MHz (WTM7 = 0) 410 s 820 s 1.64 ms 3.28 ms 6.55 ms 13.1 ms 26.2 ms 52.4 ms (WTM7 = 0) 205 s 410 s 820 s 1.64 ms 3.28 ms 6.55 ms 13.1 ms 26.2 ms (WTM7 = 0) 102 s 205 s 410 s 820 s 1.64 ms 3.28 ms 6.55 ms 13.1 ms 488 s 977 s 1.95 ms 3.91 ms 7.81 ms 15.6 ms 31.3 ms 62.5 ms Remarks 1. fW: Watch timer clock frequency (fPRS/2 or fSUB) 2. fPRS: Peripheral hardware clock frequency 3. fSUB: Subsystem clock frequency Figure 9-3. Operation Timing of Watch Timer/Interval Timer 5-bit counter 0H Start Count clock Watch timer interrupt INTWT Interrupt time of watch timer (0.5 s) Interrupt time of watch timer (0.5 s) Interval timer interrupt INTWTI Interval time (T) T Overflow Overflow Remark fW: Watch timer clock frequency Figures in parentheses are for operation with fW = 32.768 kHz (WTM7 = 1, WTM3, WTM2 = 0, 0) 244 User's Manual U17555EJ3V0UD www..com CHAPTER 9 WATCH TIMER 9.5 Cautions for Watch Timer When operation of the watch timer and 5-bit counter is enabled by the watch timer mode control register (WTM) (by setting bits 0 (WTM0) and 1 (WTM1) of WTM to 1), the interval until the first interrupt request (INTWT) is generated after the register is set does not exactly match the specification made with bits 2 and 3 (WTM2, WTM3) of WTM. Subsequently, however, the INTWT signal is generated at the specified intervals. Figure 9-4. Example of Generation of Watch Timer Interrupt Request (INTWT) (When Interrupt Period = 0.5 s) It takes 0.515625 seconds for the first INTWT to be generated (29 x 1/32768 = 0.015625 s longer). INTWT is then generated every 0.5 seconds. WTM0, WTM1 0.515625 s 0.5 s 0.5 s INTWT User's Manual U17555EJ3V0UD 245 www..com CHAPTER 10 WATCHDOG TIMER 10.1 Functions of Watchdog Timer The watchdog timer operates on the low-speed internal oscillator clock. The watchdog timer is used to detect an inadvertent program loop. If a program loop is detected, an internal reset signal is generated. Program loop is detected in the following cases. * If the watchdog timer counter overflows * If a 1-bit manipulation instruction is executed on the watchdog timer enable register (WDTE) * If data other than "ACH" is written to WDTE * If data is written to WDTE during a window close period * If the instruction is fetched from an area not set by the IMS and IXS registers (detection of an invalid check while the CPU hangs up) 246 User's Manual U17555EJ3V0UD www..com CHAPTER 10 WATCHDOG TIMER 10.2 Configuration of Watchdog Timer The watchdog timer includes the following hardware. Table 10-1. Configuration of Watchdog Timer Item Control register Configuration Watchdog timer enable register (WDTE) How the counter operation is controlled, overflow time, and window open period are set by the option byte. Table 10-2. Setting of Option Bytes and Watchdog Timer Setting of Watchdog Timer Window open period Controlling counter operation of watchdog timer Overflow time of watchdog timer Option Byte (0080H) Bits 6 and 5 (WINDOW1, WINDOW0) Bit 4 (WDTON) Bits 3 to 1 (WDCS2 to WDCS0) Remark For the option byte, see CHAPTER 22 OPTION BYTE. Figure 10-1. Block Diagram of Watchdog Timer CPU access signal CPU access error detector WDCS2 to WDCS0 of option byte (0080H) 210/fRL to 217/fRL Selector fRL/2 Clock input controller 17-bit counter Overflow signal Reset output controller Internal reset signal Count clear signal WINDOW1 and WINDOW0 of option byte (0080H) Clear, reset control Window size determination signal WDTON of option byte (0080H) Watchdog timer enable register (WDTE) Internal bus User's Manual U17555EJ3V0UD 247 www..com CHAPTER 10 WATCHDOG TIMER 10.3 Register Controlling Watchdog Timer The watchdog timer is controlled by the watchdog timer enable register (WDTE). (1) Watchdog timer enable register (WDTE) Writing ACH to WDTE clears the watchdog timer counter and starts counting again. This register can be set by an 8-bit memory manipulation instruction. Reset signal generation sets this register to 9AH or 1AHNote. Figure 10-2. Format of Watchdog Timer Enable Register (WDTE) Address: FF9BH Symbol WDTE 7 After reset: 9AH/1AHNote 6 5 R/W 4 3 2 1 0 Note The WDTE reset value differs depending on the WDTON setting value of the option byte (0080H). To operate watchdog timer, set WDTON to 1. WDTON Setting Value 0 (watchdog timer count operation disabled) 1 (watchdog timer count operation enabled) 1AH 9AH WDTE Reset Value Cautions 1. If a value other than ACH is written to WDTE, an internal reset signal is generated. If the source clock to the watchdog timer is stopped, however, an internal reset signal is generated when the source clock to the watchdog timer resumes operation. 2. If a 1-bit memory manipulation instruction is executed for WDTE, an internal reset signal is generated. If the source clock to the watchdog timer is stopped, however, an internal reset signal is generated when the source clock to the watchdog timer resumes operation. 3. The value read from WDTE is 9AH/1AH (this differs from the written value (ACH)). 248 User's Manual U17555EJ3V0UD www..com CHAPTER 10 WATCHDOG TIMER 10.4 Operation of Watchdog Timer 10.4.1 Controlling operation of watchdog timer 1. When the watchdog timer is used, its operation is specified by the option byte (0080H). * Enable counting operation of the watchdog timer by setting bit 4 (WDTON) of the option byte (0080H) to 1 (the counter starts operating after a reset release) (for details, see CHAPTER 22). WDTON 0 1 Watchdog Timer Counter Control Count operation disabled (counting stops after reset). Count operation enabled (counting starts after reset). * Set an overflow time by using bits 3 to 1 (WDCS2 to WDCS0) of the option byte (0080H) (for details, see 10.4.2 and CHAPTER 22). * Set a window open period by using bits 6 and 5 (WINDOW1 and WINDOW0) of the option byte (0080H) (for details, see 10.4.3 and CHAPTER 22). 2. After a reset release, the watchdog timer starts counting. 3. By writing "ACH" to WDTE after the watchdog timer starts counting and before the overflow time set by the option byte, the watchdog timer is cleared and starts counting again. 4. After that, write WDTE the second time or later after a reset release during the window open period. If WDTE is written during a period other than the window open period, an internal reset signal is generated. 5. If the overflow time expires without "ACH" written to WDTE, an internal reset signal is generated. User's Manual U17555EJ3V0UD 249 www..com CHAPTER 10 WATCHDOG TIMER Cautions 4. The operation of the watchdog timer in the HALT and STOP modes differs as follows depending on the set value of bit 0 (LSROSC) of the option byte. LSROSC = 0 (Internal Low-Speed Oscillator Can Be Stopped by Software) LSROSC = 1 (Internal Low-Speed Oscillator Cannot Be Stopped) Watchdog timer operation continues. In HALT mode In STOP mode Watchdog timer operation stops. If LSROSC = 0, the watchdog timer resumes counting after the HALT or STOP mode is 250 User's Manual U17555EJ3V0UD www..com CHAPTER 10 WATCHDOG TIMER 10.4.2 Setting overflow time of watchdog timer Set the overflow time of the watchdog timer by using bits 3 to 1 (WDCS2 to WDCS0) of the option byte. If an overflow occurs, an internal reset signal is generated. If "ACH" is written to WDTE during the window open period before the overflow time, the present count is cleared and the watchdog timer starts counting again. The following overflow time is set. Table 10-3. Setting of Overflow Time of Watchdog Timer WDCS2 0 0 0 0 1 1 1 1 WDCS1 0 0 1 1 0 0 1 1 WDCS0 0 1 0 1 0 1 0 1 10 Overflow Time of Watchdog Timer 2 /fRL (3.88 ms) 2 /fRL (7.76 ms) 2 /fRL (15.52 ms) 2 /fRL (31.03 ms) 2 /fRL (62.06 ms) 2 /fRL (124.12 ms) 2 /fRL (248.24 ms) 2 /fRL (496.48 ms) 17 16 15 14 13 12 11 Cautions 1. The combination of WDCS2 = WDCS1 = WDCS0 = 0 and WINDOW1 = WINDOW0 = 0 is prohibited. User's Manual U17555EJ3V0UD 251 www..com CHAPTER 10 WATCHDOG TIMER 10.4.3 Setting window open period of watchdog timer Set the window open period of the watchdog timer by using bits 6 and 5 (WINDOW1, WINDOW0) of the option Counting starts Window close period (75%) Overflow time Window open period (25%) Internal reset signal is generated if ACH is written to WDTE. Counting starts again when ACH is written to WDTE. Caution The first writing to WDTE after a reset release clears the watchdog timer, if it is made before the overflow time regardless of the timing of the writing, and the watchdog timer starts counting again. The window open period to be set is as follows. Table 10-4. Setting Window Open Period of Watchdog Timer WINDOW1 0 0 1 1 WINDOW0 0 1 0 1 25% 50% 75% 100% Window Open Period of Watchdog Timer Cautions 1. The combination of WDCS2 = WDCS1 = WDCS0 = 0 and WINDOW1 = WINDOW0 = 0 is prohibited. 252 User's Manual U17555EJ3V0UD www..com CHAPTER 10 WATCHDOG TIMER Remark If the overflow time is set to 210/fRL, the window close time and open time are as follows. Setting of Window Open Period 25% Window close time Window open time 0 to 3.56 ms 3.56 to 3.88 ms 50% 0 to 2.37 ms 2.37 to 3.88 ms 75% 0 to 0.119 ms 0.119 to 3.88 ms None 0 to 3.88 ms 100% User's Manual U17555EJ3V0UD 253 www..com CHAPTER 11 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER 11.1 Functions of Clock Output/Buzzer Output Controller The clock output controller is intended for carrier output during remote controlled transmission and clock output for supply to peripheral LSIs. The clock selected with the clock output selection register (CKS) is output. In addition, the buzzer output is intended for square-wave output of buzzer frequency selected with CKS. Figure 11-1 shows the block diagram of clock output/buzzer output controller. Figure 11-1. Block Diagram of Clock Output/Buzzer Output Controller fPRS Prescaler 8 4 fPRS/210 to fPRS/213 Selector BUZ/INTP7/P73 BZOE Output latch (P73) BCS0, BCS1 PM73 Selector fPRS to fPRS/27 fSUB Clock controller PCL/INTP6/P72 CLOE Output latch (P72) PM72 BZOE BCS1 BCS0 CLOE CCS3 CCS2 CCS1 CCS0 Clock output selection register (CKS) Internal bus 254 User's Manual U17555EJ3V0UD www..com CHAPTER 11 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER 11.2 Configuration of Clock Output/Buzzer Output Controller The clock output/buzzer output controller includes the following hardware. Table 11-1. Clock Output/Buzzer Output Controller Configuration Item Control registers Configuration Clock output selection register (CKS) Port mode register 7 (PM7) Port register 7 (P7) 11.3 Register Controlling Clock Output/Buzzer Output Controller The following two registers are used to control the clock output/buzzer output controller. * Clock output selection register (CKS) * Port mode register 7 (PM7) (1) Clock output selection register (CKS) This register sets output enable/disable for clock output (PCL) and for the buzzer frequency output (BUZ), and sets the output clock. CKS is set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears CKS to 00H. User's Manual U17555EJ3V0UD 255 www..com CHAPTER 11 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER Figure 11-2. Format of Clock Output Selection Register (CKS) Address: FF40H Symbol CKS After reset: 00H <7> BZOE 6 BCS1 R/W 5 BCS0 <4> CLOE 3 CCS3 2 CCS2 1 CCS1 0 CCS0 BZOE 0 1 BUZ output enable/disable specification Clock division circuit operation stopped. BUZ fixed to low level. Clock division circuit operation enabled. BUZ output enabled. BCS1 BCS0 BUZ output clock selection fPRS = 10 MHz fPRS = 20 MHz 19.54 kHz 9.77 kHz 4.88 kHz 2.44 kHz 0 0 1 1 0 1 0 1 fPRS/2 fPRS/2 fPRS/2 fPRS/2 10 9.77 kHz 4.88 kHz 2.44 kHz 1.22 kHz 11 12 13 CLOE 0 1 PCL output enable/disable specification Clock division circuit operation stopped. PCL fixed to low level. Clock division circuit operation enabled. PCL output enabled. CCS3 CCS2 CCS1 CCS0 PCL output clock selection fSUB = 32.768 kHz - fPRS = 10 MHz 10 MHz Note fPRS = 20 MHz Setting prohibited Note 0 0 0 0 fPRS 0 0 0 0 0 0 0 1 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 fPRS/2 fPRS/2 fPRS/2 fPRS/2 fPRS/2 fPRS/2 fPRS/2 fSUB 2 5 MHz 2.5 MHz 1.25 MHz 625 kHz 312.5 kHz 156.25 kHz 78.125 kHz 32.768 kHz - 10 MHz 5 MHz 2.5 MHz 1.25 MHz 625 kHz 312.5 kHz 156.25 kHz 3 4 5 6 7 Other than above Setting prohibited Notes 1. If the peripheral hardware clock operates on the internal high-speed oscillation clock when 1.8 V VDD < 2.7 V, setting CCS3 = CCS2 = CCS1 = CCS0 = 0 (output clock of PCL: fPRS) is prohibited. 2. The PCL output clock prohibits settings if they exceed 10 MHz. Cautions 1. Set BCS1 and BCS0 when the buzzer output operation is stopped (BZOE = 0). 2. Set CCS3 to CCS0 while the clock output operation is stopped (CLOE = 0). Remarks 1. fPRS: Peripheral hardware clock frequency 2. fSUB: Subsystem clock frequency 256 User's Manual U17555EJ3V0UD www..com CHAPTER 11 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER (2) Port mode register 7 (PM7) This register sets port 7 input/output in 1-bit units. When using the P72/INTP6/PCL pin for clock output and the P73/INTP7/BUZ pin for buzzer output, set PM72, PM73 and the output latch of P72, P73 to 0. PM7 is set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets PM7 to FFH. Figure 11-3. Format of Port Mode Register 7 (PM7) Address: FF27H Symbol PM7 7 1 After reset: FFH 6 PM76 5 PM75 R/W 4 PM74 3 PM73 2 PM72 1 PM71 0 PM70 PM7n 0 1 P7n pin I/O mode selection (n = 0 to 6) Output mode (output buffer on) Input mode (output buffer off) User's Manual U17555EJ3V0UD 257 www..com CHAPTER 11 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER 11.4 Clock Output/Buzzer Output Controller Operations 11.4.1 Clock output operation The clock pulse is output as the following procedure. <1> Select the clock pulse output frequency with bits 0 to 3 (CCS0 to CCS3) of the clock output selection register (CKS) (clock pulse output in disabled status). <2> Set bit 4 (CLOE) of CKS to 1 to enable clock output. Remark The clock output controller is designed not to output pulses with a small width during output enable/disable switching of the clock output. As shown in Figure 11-4, be sure to start output from the low period of the clock (marked with * in the figure). When stopping output, do so after the high-level period of the clock. Figure 11-4. Remote Control Output Application Example CLOE * Clock output * 11.4.2 Operation as buzzer output The buzzer frequency is output as the following procedure. <1> Select the buzzer output frequency with bits 5 and 6 (BCS0, BCS1) of the clock output selection register (CKS) (buzzer output in disabled status). <2> Set bit 7 (BZOE) of CKS to 1 to enable buzzer output. 258 User's Manual U17555EJ3V0UD www..com CHAPTER 12 A/D CONVERTER 12.1 Function of A/D Converter The A/D converter converts an analog input signal into a digital value, and consists of up to eight channels (ANI0 to ANI8Note) with a resolution of 10 bits. The A/D converter has the following function. * 10-bit resolution A/D conversion 10-bit resolution A/D conversion is carried out repeatedly for one channel selected from analog inputs ANI0 to ANI8. Each time an A/D conversion operation ends, an interrupt request (INTAD) is generated. Figure 12-1. Block Diagram of A/D Converter AVREF ADCS bit P80/ANI0 P81/ANI1 P82/ANI2 P83/ANI3 P84/ANI4 P85/ANI5 P86/ANI6 P87/ANI7 P90/ANI8Note1 Sample & hold circuit Selector AVSS Successive approximation register (SAR) Tap selector Voltage comparator AVSS Controller A/D conversion result register (ADCR) INTAD 4 4 5 Note2 ADS3 ADS2 ADS1 ADS0 ADPC3 ADPC2 ADPC1 ADPC0 ADCS FR2 FR1 FR0 LV1 LV0 ADCE Analog input channel specification register (ADS) A/D port configuration register (ADPC) Internal bus A/D converter mode register (ADM) Notes 1. P90/ANI8 is PD78F0884, 78F0885, and 78F0886 only. User's Manual U17555EJ3V0UD 259 www..com CHAPTER 12 A/D CONVERTER 12.2 Configuration of A/D Converter The A/D converter includes the following hardware. AVREF P-ch ADCS Series resistor string AVSS (4) Voltage comparator 260 User's Manual U17555EJ3V0UD www..com CHAPTER 12 A/D CONVERTER (7) 8-bit A/D conversion result register (ADCRH) The A/D conversion result is loaded from the successive approximation register to this register each time A/D conversion is completed, and the ADCRH register stores the higher 8 bits of the A/D conversion result. Caution When data is read from ADCR and ADCRH, a wait cycle is generated. Do not read data from ADCR and ADCRH when the CPU is operating on the subsystem clock and the peripheral hardware clock is stopped. For details, see CHAPTER 30 CAUTIONS FOR WAIT. (8) Controller User's Manual U17555EJ3V0UD 261 www..com CHAPTER 12 A/D CONVERTER 12.3 Registers Used in A/D Converter The A/D converter uses the following six registers. * A/D converter mode register (ADM) * A/D port configuration register (ADPC) * Analog input channel specification register (ADS) * Port mode register 8 (PM8) * Port mode register 9 (PM9)Note * 10-bit A/D conversion result register (ADCR) * 8-bit A/D conversion result register (ADCRH) Note PM9 is PD78F0884, 78F0885, and 78F0886 only. (1) A/D converter mode register (ADM) This register sets the conversion time for analog input to be A/D converted, and starts/stops conversion. ADM can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 12-3. Format of A/D Converter Mode Register (ADM) Address: FF2AH Symbol ADM <7> ADCS After reset: 00H 6 0 R/W 5 FR2 Note 1 4 FR1 Note 1 3 FR0 Note 1 2 LV1 Note 1 1 LV0 Note 1 <0> ADCE ADCS 0 1 A/D conversion operation control Stops conversion operation Enables conversion operation ADCE 0 1 Stops comparator operation Comparator operation controlNote 2 Enables comparator operation (comparator: 1/2AVREF operation) Notes 1. For details of FR2 to FR0, LV1, LV0, and A/D conversion, see Table 12-2 A/D Conversion Time Selection. The operation of the comparator is controlled by ADCS and ADCE, and it takes 1 s from operation start to operation stabilization. Therefore, when ADCS is set to 1 after 1 s or more has elapsed from the time ADCE is set to 1, the conversion result at that time has priority over the first conversion result. Otherwise, ignore data of the first conversion. 262 User's Manual U17555EJ3V0UD www..com CHAPTER 12 A/D CONVERTER Table 12-1. Settings of ADCS and ADCE ADCS 0 ADCE 0 1 A/D Conversion Operation Stop status (DC power consumption path does not exist) Conversion waiting mode (comparator: 1/2AVREF operation, only comparator consumes power) 1 0 1 Conversion mode (comparator operation stopped Note 0 ) 1 Conversion mode (comparator: 1/2AVREF operation) Note Ignore data of the first conversion because it is not guaranteed range. Figure 12-4. Timing Chart When Comparator Is Used ADCE Comparator Conversion operation ADCS Note Conversion waiting Conversion operation Conversion stopped Comparator: 1/2AVREF operation Note To stabilize the internal circuit, the time from the rising of the ADCE bit to the rising of the ADCS bit must be 1 s or longer. Cautions 1. A/D conversion must be stopped before rewriting bits FR0 to FR2, LV1, and LV0 to values other than the identical data. 2. If data is written to ADM, a wait cycle is generated. Do not write data to ADM when the CPU is operating on the subsystem clock and the peripheral hardware clock is stopped. For details, see CHAPTER 30 CAUTIONS FOR WAIT. User's Manual U17555EJ3V0UD 263 www..com CHAPTER 12 A/D CONVERTER Table 12-2. A/D Conversion Time Selection (1) 2.7 V AVREF 5.5 V A/D Converter Mode Register (ADM) FR2 0 0 0 0 1 1 FR1 0 0 1 1 0 0 FR0 0 1 0 1 0 1 LV1 0 0 0 0 0 0 LV0 0 0 0 0 0 0 264/fPRS 176/fPRS 132/fPRS 88/fPRS 66/fPRS 44/fPRS 33.0 s 22.0 s 16.5 s 11.0 s Note Conversion Time Selection fPRS = 4 MHz Setting prohibited Conversion Clock (fAD) fPRS = 10 MHz 26.4 s 17.6 s 13.2 s 8.8 s 6.6 s Note fPRS = 20 MHz 13.2 s 8.8 s 6.6 s Note fPRS/12 fPRS/8 fPRS/6 fPRS/4 fPRS/3 fPRS/2 Note Setting prohibited Note Setting prohibited Other than above Setting prohibited Note This can be set only when 4.0 V AVREF 5.5 V. (2) 2.3 V AVREF < 2.7 V A/D Converter Mode Register (ADM) FR2 0 0 0 0 1 FR1 0 0 1 1 0 FR0 0 1 0 1 0 LV1 0 0 0 0 0 LV0 1 1 1 1 1 480/fPRS 320/fPRS 240/fPRS 160/fPRS 120/fPRS 60.0 s 40.0 s 30.0 s Conversion Time Selection fPRS = 2 MHz Setting prohibited fPRS = 5 MHz Setting prohibited 64.0 s 48.0 s 32.0 s Setting prohibited fPRS/12 fPRS/8 fPRS/6 fPRS/4 fPRS/3 Conversion Clock (fAD) Other than above Setting prohibited Cautions 1. Set the conversion times with the following conditions. * 4.0 V AVREF 5.5 V: fAD = 0.6 to 3.6 MHz * 2.7 V AVREF < 4.0 V: fAD = 0.6 to 1.8 MHz * 2.3 V AVREF < 2.7 V: fAD = 0.6 to 1.48 MHz 2. 3. When rewriting FR2 to FR0, LV1, and LV0 to other than the same data, stop A/D conversion once (ADCS = 0) beforehand. Change LV1 and LV0 from the default value, when 2.3 V AVREF < 2.7 V. The above conversion time does not include clock frequency errors. Select conversion time, taking clock frequency errors into consideration. Remark fPRS: Peripheral hardware clock frequency 264 User's Manual U17555EJ3V0UD www..com CHAPTER 12 A/D CONVERTER Figure 12-5. A/D Converter Sampling and A/D Conversion Timing ADCS 1 or ADS rewrite ADCS Sampling timing INTAD Wait periodNote SAR clear Sampling time Successive conversion time Transfer SAR to ADCR, clear INTAD generation Sampling time Conversion time Conversion time Note For details of wait period, see CHAPTER 30 CAUTIONS FOR WAIT. (2) 10-bit A/D conversion result register (ADCR) This register is a 16-bit register that stores the A/D conversion result. The lower 6 bits are fixed to 0. Each time A/D conversion ends, the conversion result is loaded from the successive approximation register, and is stored in ADCR in order starting from bit 7 of FF19H. FF19H indicates the higher 8 bits of the conversion result, and FF18H indicates the lower 2 bits of the conversion result. ADCR can be read by a 16-bit memory manipulation instruction. Reset signal generation clears this register to 0000H. Figure 12-6. Format of 10-Bit A/D Conversion Result Register (ADCR) Address: FF18H, FF19H Symbol ADCR After reset: 0000H FF19H R FF18H 0 0 0 0 0 0 Cautions 1. When writing to the A/D converter mode register (ADM), analog input channel specification register (ADS), and A/D port configuration register (ADPC), the contents of ADCR may become undefined. Read the conversion result following conversion completion before writing to ADM, ADS, and ADPC. Using timing other than the above may cause an incorrect conversion result to be read. 2. If data is read from ADCR, a wait cycle is generated. Do not read data from ADCR when the CPU is operating on the subsystem clock and the peripheral hardware clock is stopped. For details, see CHAPTER 30 CAUTIONS FOR WAIT. User's Manual U17555EJ3V0UD 265 www..com CHAPTER 12 A/D CONVERTER (3) 8-bit A/D conversion result register (ADCRH) This register is an 8-bit register that stores the A/D conversion result. The higher 8 bits of 10-bit resolution are stored. ADCRH can be read by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 12-7. Format of 8-Bit A/D Conversion Result Register (ADCRH) Address: FF19H Symbol ADCRH 7 After reset: 00H 6 5 R 4 3 2 1 0 Cautions 1. When writing to the A/D converter mode register (ADM), analog input channel specification register (ADS), and A/D port configuration register (ADPC), the contents of ADCRH may become undefined. Read the conversion result following conversion completion before writing to ADM, ADS, and ADPC. Using timing other than the above may cause an incorrect conversion result to be read. 2. If data is read from ADCRH, a wait cycle is generated. Do not read data from ADCRH when the CPU is operating on the subsystem clock and the peripheral hardware clock is stopped. For details, see CHAPTER 30 CAUTIONS FOR WAIT. 266 User's Manual U17555EJ3V0UD www..com CHAPTER 12 A/D CONVERTER (4) Analog input channel specification register (ADS) This register specifies the input port of the analog voltage to be A/D converted. ADS can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Address: FF2BH Symbol ADS 7 0 After reset: 00H 6 0 R/W 5 0 4 0 3 ADS3 2 ADS2 1 ADS1 0 ADS0 ADS3 0 0 0 0 0 0 0 0 1 ADS2 0 0 0 0 1 1 1 1 0 ADS1 0 0 1 1 0 0 1 1 0 ADS0 0 1 0 1 0 1 0 1 0 ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 ANI8 Note Analog input channel specification Note ANI8 is PD78F0884, 78F0885, and 78F0886 only. User's Manual U17555EJ3V0UD 267 www..com CHAPTER 12 A/D CONVERTER (5) A/D port configuration register (ADPC) Address: FF22H Symbol ADPC 7 0 Figure 12-9. Format of A/D Port Configuration Register (ADPC) After reset: 00H 6 0 R/W 5 0 4 0 3 ADPC3 2 ADPC2 1 ADPC1 0 ADPC0 ADPC3 ADPC2 ADPC1 ADPC0 Analog input (A)/ digital I/O (D) switching P90/ANI8 P87/ANI7 P86/ANI6 P85/ANI5 P84/ANI4 P83/ANI3 P82/ANI2 P81/ANI1 P80/ANI0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 A A A A A A A A A D A A A A A A A A D D A A A A A A A D D D A A A A A A D D D D A A A A A D D D D D A A A A D D D D D D A A A D D D D D D D A A D D D D D D D D A D D D D D D D D D Other than above Setting prohibited Cautions 1. Set the channel to be used for A/D conversion in the input mode by using port mode register 8, 9 (PM8, PM9). 2. If data is written to ADPC, a wait cycle is generated. Do not write data to ADPC when the CPU is operating on the subsystem clock and the peripheral hardware clock is stopped. For details, see CHAPTER 30 CAUTIONS FOR WAIT. 3. P90/ANI8 is PD78F0884, 78F0885, and 78F0886 only. 268 User's Manual U17555EJ3V0UD www..com CHAPTER 12 A/D CONVERTER (6) Port mode register 8 (PM8) When using the P80/ANI0 to P87/ANI7 pins for analog input port, set PM80 to PM87 to 1. The output latches of P80 to P87 at this time may be 0 or 1. Address: FF28H Symbol PM8 7 PM87 After reset: FFH 6 PM86 R/W 5 PM85 4 PM84 3 PM83 2 PM82 1 PM81 0 PM80 PM8n 0 1 P8n pin I/O mode selection (n = 0 to 7) Output mode (Output buffer on) Input mode (Output buffer off) (7) Port mode register 9 (PM9)Note When using the P90/ANI8 pin for analog input port, set PM90 to 1. The output latches of P90 at this time may be 0 or 1. If PM90 is set to 0, they cannot be used as analog input port pin. PM9 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to FFH. Figure 12-11. Format of Port Mode Register 9 (PM9) Address: FF29H Symbol PM9 7 1 After reset: FFH 6 1 R/W 5 1 4 1 3 1 2 1 1 1 0 PM90 PM90 0 1 Output mode (Output buffer on) Input mode (Output buffer off) P90 pin I/O mode selection Note PM9 is PD78F0884, 78F0885, and 78F0886 only. User's Manual U17555EJ3V0UD 269 www..com CHAPTER 12 A/D CONVERTER P80/ANI0 to P87/ANI7, P90/ANI8 pins are as shown below depending on the settings of ADPC, ADS, PM8 and PM9. ADPC Table 12-3. Setting Functions of P80/ANI0 to P87/ANI7, P90/ANI8 Pins PM8, PM9 ADS P80/ANI0 to P87/ANI7, P90/ANI8 Pins Analog input selection Input mode Selects ANI. Does not select ANI. Output mode Selects ANI. Does not select ANI. Digital I/O selection Input mode Output mode - - Digital input Digital output Analog input (to be converted) Analog input (not to be converted) Setting prohibited Caution P90/ANI8 is PD78F0884, 78F0885, and 78F0886 only. 270 User's Manual U17555EJ3V0UD www..com CHAPTER 12 A/D CONVERTER 12.4 A/D Converter Operations User's Manual U17555EJ3V0UD 271 www..com CHAPTER 12 A/D CONVERTER Figure 12-12. Basic Operation of A/D Converter Conversion time Sampling time A/D converter operation Sampling A/D conversion SAR Undefined Conversion result ADCR Conversion result INTAD A/D conversion operations are performed continuously until bit 7 (ADCS) of the A/D converter mode register (ADM) is reset (0) by software. If a write operation is performed to the analog input channel specification register (ADS) during an A/D conversion operation, the conversion operation is initialized, and if the ADCS bit is set (1), conversion starts again from the beginning. Reset signal generation clears the A/D conversion result register (ADCR, ADCRH) to 0000H or 00H. 272 User's Manual U17555EJ3V0UD www..com CHAPTER 12 A/D CONVERTER 12.4.2 Input voltage and conversion results ADCR = SAR x 64 or (ADCR - 0.5) x where, INT( ): VAIN: AVREF: SAR: Function which returns integer part of value in parentheses Analog input voltage AVREF pin voltage Successive approximation register ADCR: A/D conversion result register (ADCR) value Note P90/ ANI8 is PD78F0884, 78F0885, and 78F0886 only. Figure 12-13 shows the relationship between the analog input voltage and the A/D conversion result. Figure 12-13. Relationship Between Analog Input Voltage and A/D Conversion Result SAR ADCR 1023 FFC0H 1022 FF80H 1021 A/D conversion result (ADCR) 3 FF40H 00C0H 2 0080H 1 0040H 0 1 1 3 2 5 3 2048 1024 2048 1024 2048 1024 2043 1022 2045 1023 2047 1 2048 1024 2048 1024 2048 0000H Input voltage/AVREF User's Manual U17555EJ3V0UD 273 www..com CHAPTER 12 A/D CONVERTER 12.4.3 A/D converter operation mode The operation mode of the A/D converter is the select mode. One channel of analog input is selected from ANI0 to ANI8 by the analog input channel specification register (ADS) and A/D conversion is executed. (1) A/D conversion operation By setting bit 7 (ADCS) of the A/D converter mode register (ADM) to 1, the A/D conversion operation of the voltage, which is applied to the analog input pin specified by the analog input channel specification register (ADS), is started. When A/D conversion has been completed, the result of the A/D conversion is stored in the A/D conversion result Rewriting ADM ADCS = 1 At this time, the Rewriting ADS ADCS = 0 A/D conversion ANIn ANIn ANIn ANIm ANIm Stopped Conversion result immediately before is retained Conversion is stopped Conversion result immediately before is retained ADCR, ADCRH ANIn ANIn ANIm INTAD Caution ANI8 is PD78F0884, 78F0885, and 78F0886 only. Remarks 1. n = 0 to 8 2. m = 0 to 8 274 User's Manual U17555EJ3V0UD www..com CHAPTER 12 A/D CONVERTER The setting methods are described below. <1> Set bit 0 (ADCE) of the A/D converter mode register (ADM) to 1. <2> Set the channel to be used in the analog input mode by using bits 3 to 0 (ADPC3 to ADPC0) of the A/D port configuration register (ADPC) and bits 7 to 0 (PM87 to PM80) of port mode register 8 (PM8), bit 0 (PM90) of port mode register 9 (PM9)Note. <3> Select conversion time by using bits 5 to 1 (FR2 to FR0, LV1, and LV0) of ADM. <4> Select a channel to be used by using bits 3 to 0 (ADS3 to ADS0) of the analog input channel specification register (ADS). <5> Set bit 7 (ADCS) of ADM to 1 to start A/D conversion. <6> When one A/D conversion has been completed, an interrupt request signal (INTAD) is generated. <7> Transfer the A/D conversion data to the A/D conversion result register (ADCR, ADCRH). User's Manual U17555EJ3V0UD 275 www..com CHAPTER 12 A/D CONVERTER 12.5 How to Read A/D Converter Characteristics Table Here, special terms unique to the A/D converter are explained. (1) Resolution This is the minimum analog input voltage that can be identified. That is, the percentage of the analog input voltage per bit of digital output is called 1LSB (Least Significant Bit). The percentage of 1LSB with respect to the full scale is expressed by %FSR (Full Scale Range). 1LSB is as follows when the resolution is 10 bits. 1LSB = 1/210 = 1/1024 = 0.098%FSR Accuracy has no relation to resolution, but is determined by overall error. (2) Overall error This shows the maximum error value between the actual measured value and the theoretical value. Zero-scale error, full-scale error, integral linearity error, and differential linearity errors that are combinations of these express the overall error. Note that the quantization error is not included in the overall error in the characteristics table. (3) Quantization error When analog values are converted to digital values, a 1/2LSB error naturally occurs. In an A/D converter, an analog input voltage in a range of 1/2LSB is converted to the same digital code, so a quantization error cannot be avoided. Note that the quantization error is not included in the overall error, zero-scale error, full-scale error, integral linearity error, and differential linearity error in the characteristics table. Figure 12-15. Overall Error 1......1 Figure 12-16. Quantization Error 1......1 Ideal line Digital output Overall error Digital output 1/2LSB Quantization error 1/2LSB 0......0 0 Analog input AVREF 0......0 0 Analog input AVREF (4) Zero-scale error This shows the difference between the actual measurement value of the analog input voltage and the theoretical value (1/2LSB) when the digital output changes from 0......000 to 0......001. If the actual measurement value is greater than the theoretical value, it shows the difference between the actual measurement value of the analog input voltage and the theoretical value (3/2LSB) when the digital output changes from 0......001 to 0......010. 276 User's Manual U17555EJ3V0UD www..com CHAPTER 12 A/D CONVERTER (5) Full-scale error This shows the difference between the actual measurement value of the analog input voltage and the theoretical value (Full-scale - 3/2LSB) when the digital output changes from 1......110 to 1......111. (6) Integral linearity error This shows the degree to which the conversion characteristics deviate from the ideal linear relationship. It expresses the maximum value of the difference between the actual measurement value and the ideal straight line when the zero-scale error and full-scale error are 0. (7) Differential linearity error While the ideal width of code output is 1LSB, this indicates the difference between the actual measurement value and the ideal value. Figure 12-17. Zero-Scale Error 111 Digital output (Lower 3 bits) Full-scale error Figure 12-18. Full-Scale Error Ideal line 011 Digital output (Lower 3 bits) 111 010 001 000 0 1 2 3 AVREF Analog input (LSB) 110 Zero-scale error 101 Ideal line 000 0 AVREF-3 AVREF-2 AVREF-1 AVREF Analog input (LSB) Figure 12-19. Integral Linearity Error 1......1 Ideal line Digital output Figure 12-20. Differential Linearity Error 1......1 Ideal 1LSB width Digital output 0......0 0 Integral linearity error Analog input AVREF Differential linearity error 0......0 0 Analog input AVREF (8) Conversion time This expresses the time from the start of sampling to when the digital output is obtained. The sampling time is included in the conversion time in the characteristics table. (9) Sampling time This is the time the analog switch is turned on for the analog voltage to be sampled by the sample & hold circuit. Sampling time Conversion time User's Manual U17555EJ3V0UD 277 www..com CHAPTER 12 A/D CONVERTER 278 User's Manual U17555EJ3V0UD www..com CHAPTER 12 A/D CONVERTER Figure 12-21. Analog Input Pin Connection If there is a possibility that noise equal to or higher than AVREF or equal to or lower than AVSS may enter, clamp with a diode with a small VF value (0.3 V or lower). Reference voltage input AVREF ANI0 to ANI8 Note C = 100 to 1,000 pF AVSS VSS Note ANI8 is PD78F0884, 78F0885, 78F0886 only. (5) P80/ANI0 to P87/ANI7, P90/ANI8 <1> The analog input pins (ANI0 to ANI8) are also used as I/O port pins (P80 to P87, P90). When A/D conversion is performed with any of ANI0 to ANI8 selected, do not access P80 to P87 and P90 while conversion is in progress; otherwise the conversion resolution may be degraded. It is recommended to select pins used as P80 to P87, P90 starting with the P80/ANI0 that is the furthest from AVREF. <2> If a digital pulse is applied to the pins adjacent to the pins currently used for A/D conversion, the expected value of the A/D conversion may not be obtained due to coupling noise. Therefore, do not apply a pulse to the pins adjacent to the pin undergoing A/D conversion. (6) Input impedance of ANI0 to ANI8 pins This A/D converter charges a sampling capacitor for sampling during sampling time. Therefore, only a leakage current flows when sampling is not in progress, and a current that charges the capacitor flows during sampling. Consequently, the input impedance fluctuates depending on whether sampling is in progress, and on the other states. To make sure that sampling is effective, however, it is recommended to keep the output impedance of the analog input source to within 10 k, and to connect a capacitor of about 100 pF to the ANI0 to ANI8 pins (see Figure 1221). (7) AVREF pin input impedance A series resistor string of several tens of k is connected between the AVREF and AVSS pins. Therefore, if the output impedance of the reference voltage source is high, this will result in a series connection to the series resistor string between the AVREF and AVSS pins, resulting in a large reference voltage error. Caution P90/ANI8 is PD78F0884, 78F0885, and 78F0886 only. User's Manual U17555EJ3V0UD 279 www..com CHAPTER 12 A/D CONVERTER (8) Interrupt request flag (ADIF) The interrupt request flag (ADIF) is not cleared even if the analog input channel specification register (ADS) is changed. Therefore, if an analog input pin is changed during A/D conversion, the A/D conversion result and ADIF for the pre-change analog input may be set just before the ADS rewrite. Caution is therefore required since, at this time, when ADIF is read immediately after the ADS rewrite, ADIF is set despite the fact A/D conversion for the postchange analog input has not ended. When A/D conversion is stopped and then resumed, clear ADIF before the A/D conversion operation is resumed. Figure 12-22. Timing of A/D Conversion End Interrupt Request Generation ADS rewrite (start of ANIn conversion) ADS rewrite (start of ANIm conversion) ADIF is set but ANIm conversion has not ended. A/D conversion ANIn ANIn ANIm ANIm ADCR ANIn ANIn ANIm ANIm ADIF Remarks 1. n = 0 to 8 2. m = 0 to 8 (9) Conversion results just after A/D conversion start The first A/D conversion value immediately after A/D conversion starts may not fall within the rating range if the ADCS bit is set to 1 within 1 s after the ADCE bit was set to 1, or if the ADCS bit is set to 1 with the ADCE bit = 0. Take measures such as polling the A/D conversion end interrupt request (INTAD) and removing the first conversion result. (10) A/D conversion result register (ADCR, ADCRH) read operation When a write operation is performed to the A/D converter mode register (ADM), analog input channel specification register (ADS), and A/D port configuration register (ADPC), the contents of ADCR and ADCRH may become undefined. Read the conversion result following conversion completion before writing to ADM, ADS, and ADPC. Using a timing other than the above may cause an incorrect conversion result to be read. Caution ANI8 is PD78F0884, 78F0885, and 78F0886 only. 280 User's Manual U17555EJ3V0UD www..com CHAPTER 12 A/D CONVERTER (11) Internal equivalent circuit The equivalent circuit of the analog input block is shown below. Figure 12-23. Internal Equivalent Circuit of ANIn Pin R1 ANIn C1 C2 Table 12-4. Resistance and Capacitance Values of Equivalent Circuit (Reference Values) AVREF 4.0 V AVREF 5.5 V 2.7 V AVREF < 4.0 V 2.3 V AVREF < 2.7 V R1 8.1 k 31 k 381 k C1 8 pF 8 pF 8 pF C2 5 pF 5 pF 5 pF Caution ANI8 is PD78F0884, 78F0885, and 78F0886 only. Remarks 1. The resistance and capacitance values shown in Table 12-4 are not guaranteed values. 2. n = 0 to 8 User's Manual U17555EJ3V0UD 281 www..com CHAPTER 13 SERIAL INTERFACES UART60 AND UART61 The 78K0/FC2 incorporate serial interfaces UART60 and UART61. 13.1 Functions of Serial Interfaces UART60 and UART61 Serial interfaces UART60 and UART61 have the following two modes. (1) Operation stop mode This mode is used when serial communication is not executed and can enable a reduction in the power consumption. For details, see 13.4.1 Operation stop mode. (2) Asynchronous serial interface (UART) mode This mode supports the LIN (Local Interconnect Network)-bus. The functions of this mode are outlined below. For details, see 13.4.2 generator. 282 User's Manual U17555EJ3V0UD www..com CHAPTER 13 SERIAL INTERFACES UART60 AND UART61 Cautions 6. If data is continuously transmitted, the communication timing from the stop bit to the next start bit is extended two operating clocks of the macro. However, this does not affect the result of communication because the reception side initializes the timing when it has detected a start bit. Do not use the continuous transmission function if the interface is used in LIN communication operation. Remarks 1. LIN stands for Local Interconnect Network and is a low-speed (1 to 20 kbps) serial communication protocol intended to aid the cost reduction of an automotive network. LIN communication is single-master communication, and up to 15 slaves can be connected to one master. The LIN slaves are used to control the switches, actuators, and sensors, and these are connected to the LIN master via the LIN network. Normally, the LIN master is connected to a network such as CAN (Controller Area Network). In addition, the LIN bus uses a single-wire method and is connected to the nodes via a transceiver that complies with ISO9141. n the LIN protocol, the master transmits a frame with baud rate information and the slave receives it and corrects the baud rate error. Therefore, communication is possible when the baud rate error in the slave is 15% or less. 2. n = 0, 1 Figures 13-1 and 13-2 outline the transmission and reception operations of LIN. Wakeup signal frame Figure 13-1. LIN Transmission Operation Sync break field Sync field Identifier field Data field Data field Checksum field LIN bus 13-bitNote 2 SBF transmission 55H Data Data Data Data transmission transmission transmission transmission transmission 8 bits Note 1 TXD6n INTST6n Note 3 Notes 1. 2. The wakeup signal frame is substituted by 80H transmission in the 8-bit mode. The sync break field is output by hardware. The output width is the bit length set by bits 4 to 2 (SBL62n to SBL60n) of asynchronous serial interface control register 6n (ASICL6n). If more precise output width adjustment is necessary, use baud rate generator control register 6n (BRGC6n) (see 13.4.2 (2) (h) SBF transmission). 3. Remark INTST6n is output on completion of each transmission. It is also output when SBF is transmitted. The interval between each field is controlled by software. n = 0, 1 User's Manual U17555EJ3V0UD 283 www..com CHAPTER 13 SERIAL INTERFACES UART60 AND UART61 Wakeup signal frame LIN bus Figure 13-2. LIN Reception Operation Sync break field Sync field Identifer field Data field Data field Checksum field 13-bit SBF reception <2> RXD6n Disable Enable <3> Reception interrupt (INTSR6n) <1> Edge detection (INTPn) SF reception ID reception Data reception Data reception Data reception <5> <4> Capture timer Disable Enable Reception processing is as follows. <1> The wakeup signal is detected at the edge of the pin, and enables UART6n and sets the SBF reception mode. <2> Reception continues until the STOP bit is detected. When an SBF with low-level data of 11 bits or more has been detected, it is assumed that SBF reception has been completed correctly, and an interrupt signal is output. If an SBF with low-level data of less than 11 bits has been detected, it is assumed that an SBF reception error has occurred. The interrupt signal is not output and the SBF reception mode is restored. <3> If SBF reception has been completed correctly, an interrupt signal is output. Start 16-bit timer/event counter 00 by the SBF reception end interrupt servicing and measure the bit interval (pulse width) of the sync field (see 6.4.3 Pulse width measurement operation). Detection of errors OVE6n, PE6n, and FE6n is suppressed, and error detection processing of UART communication and data transfer of the shift register and RXB6n is not performed. The shift register holds the reset value FFH. <4> Calculate the baud rate error from the bit length of the sync field, disable UART6n after SF reception, and then re-set baud rate generator control register 6n (BRGC6n). <5> Distinguish the checksum field by software. Also perform processing by software to initialize UART6n after reception of the checksum field and to set the SBF reception mode again. Remark n = 0, 1 284 User's Manual U17555EJ3V0UD www..com CHAPTER 13 SERIAL INTERFACES UART60 AND UART61 Figure 13-3 and 13-4 show the port configuration for LIN reception operation. The wakeup signal transmitted from the LIN master is received by detecting the edge of the external interrupt (INTP0 and INTP1). The length of the sync field transmitted from the LIN master can be measured using the external event capture operation of 16-bit timer/event counter 00, and the baud rate error can be calculated. The input source of the reception port input (RxD60 and RxD61) can be input to the external interrupt (INTP0 and INTP1) and 16-bit timer/event counter 00 by port input switch control (ISC), without connecting RxD60, RxD61, INTP0, INTP1, TI010 externally. Figure 13-3. Port Configuration for LIN Reception Operation Selector P14/RxD60 RxD60 input Port mode (PM14) Output latch (P14) Selector Selector P01/TI010 TI010 input Port mode (PM01) Output latch (P01) Selector P120/INTP0 Port input switch control (ISC1) INTP0 input Port mode (PM120) Output latch (P120) Port input switch control (ISC3) Remark ISC1, ISC3: Bits 1 and 3 of the input switch control register (ISC) (see Figure 13-19) The peripheral functions used in the LIN communication operation are shown below. User's Manual U17555EJ3V0UD 285 www..com CHAPTER 13 SERIAL INTERFACES UART60 AND UART61 Figure 13-4. Port Configuration for LIN Reception Operation (UART61) Selector P11/RxD61 RxD61 input Port mode (PM11) Output latch (P11) Selector Selector P30/INTP1 INTP1 input Port mode (PM30) Output latch4 (P30) Port input switch control (ISC4) Remark ISC4: Bit 4 of the input switch control register (ISC) (see Figure 13-19) The peripheral functions used in the LIN communication operation are shown below. 286 User's Manual U17555EJ3V0UD www..com CHAPTER 13 SERIAL INTERFACES UART60 AND UART61 13.2 Configurations of Serial Interface UART60 and UART61 Serial interfaces UART60 and UART61 include the following hardware. Table 13-1. Configurations of Serial Interface UART60 and UART61 Item Registers Receive buffer register 6n (RXB6n) Receive shift register 6n (RXS6n) Transmit buffer register 6n (TXB6n) Transmit shift register 6n (TXS6n) Control registers Asynchronous serial interface operation mode register 6n (ASIM6n) Asynchronous serial interface reception error status register 6n (ASIS6n) Asynchronous serial interface transmission status register 6n (ASIF6n) Clock selection register 6n (CKSR6n) Baud rate generator control register 6n (BRGC6n) Asynchronous serial interface control register 6n (ASICL6n) Input switch control register (ISC) Port mode register 1 (PM1) Port register 1 (P1) Configuration Remark n = 0, 1 User's Manual U17555EJ3V0UD 287 www..com Selector 288 fPRS fPRS/2 fPRS/22 fPRS/23 fPRS/24 fPRS/25 fPRS/26 fPRS/27 fPRS/28 fPRS/29 fPRS/210 8-bit timer/ event counter 50 output Asynchronous serial interface operation mode register 60 (ASIM60) Figure 13-5. Block Diagram of Serial Interface UART60 TI010, INTP0 Filter INTSR60 INTSRE60 RXD60/P14 Reception control Receive shift register 60 (RXS60) CHAPTER 13 SERIAL INTERFACES UART60 AND UART61 Asynchronous serial interface reception error status register 60 (ASIS60) Baud rate generator Reception unit Internal bus Asynchronous serial interface control register 60 (ASICL60) Receive buffer register 60 (RXB60) User's Manual U17555EJ3V0UD Baud rate generator control register 60 (BRGC60) 8 Asynchronous serial Clock selection interface transmission register 60 (CKSR60) status register 60 (ASIF60) 8 Baud rate generator Asynchronous serial interface control register 60 (ASICL60) Transmit buffer register 60 (TXB60) INTST60 Transmission control Transmit shift register 60 (TXS60) TXD60/P13 Registers Output latch P13 Transmission unit PM13 Note Selectable with input switch control register (ISC) www..com Figure 13-6. Block Diagram of Serial Interface UART61 Filter INTSR61 INTSRE61 RXD61/P11/SI10 Reception control Receive shift register 61 (RXS61) Asynchronous serial interface control register 61 (ASICL61) Receive buffer register 61 (RXB61) fPRS fPRS/2 fPRS/22 fPRS/23 fPRS/24 fPRS/25 fPRS/26 fPRS/27 fPRS/28 fPRS/29 fPRS/210 8-bit timer/ event counter 50 output Selector Asynchronous serial interface operation mode register 61 (ASIM61) Asynchronous serial interface reception error status register 61 (ASIS61) Baud rate generator Reception unit Internal bus CHAPTER 13 SERIAL INTERFACES UART60 AND UART61 Baud rate generator control register 61 (BRGC61) 8 Asynchronous serial Clock selection interface transmission register 61 (CKSR61) status register 61 (ASIF61) 8 Baud rate generator Asynchronous serial interface control register 61 (ASICL61) Transmit buffer register 61 (TXB61) User's Manual U17555EJ3V0UD INTST61 Transmission control Transmit shift register 61 (TXS61) TXD61/P10/SCK10 Registers Output latch P10 Transmission unit PM10 289 www..com CHAPTER 13 SERIAL INTERFACES UART60 AND UART61 (1) Receive buffer register 6n (RXB6n) This 8-bit register stores parallel data converted by receive shift register 6n (RXS6n). Each time 1 byte of data has been received, new receive data is transferred to this register from RXS6n. If the data length is set to 7 bits, data is transferred as follows. * In LSB-first reception, the receive data is transferred to bits 0 to 6 of RXB6n and the MSB of RXB6n is always 0. * In MSB-first reception, the receive data is transferred to bits 1 to 7 of RXB6n and the LSB of RXB6n is always 0. If an overrun error (OVE6n) occurs, the receive data is not transferred to RXB6n. RXB6n can be read by an 8-bit memory manipulation instruction. No data can be written to this register. Reset signal generation sets this register to FFH. (2) Receive shift register 6n (RXS6n) This register converts the serial data input to the RXD6n pins into parallel data. RXS6n cannot be directly manipulated by a program. (3) Transmit buffer register 6n (TXB6n) This buffer register is used to set transmit data. Transmission is started when data is written to TXB6n. This register can be read or written by an 8-bit memory manipulation instruction. Reset signal generation sets this register to FFH. Cautions 1. Do not write data to TXB6n when bit 1 (TXBF6n) of asynchronous serial interface transmission status register 6n (ASIF6n) is 1. 2. Do not refresh (write the same value to) TXB6n by software during a communication operation (when bits 7 and 6 (POWER6n, TXE6n) of asynchronous serial interface operation mode register 6n (ASIM6n) are 1 or when bits 7 and 5 (POWER6n, RXE6n) of ASIM6n are 1). 290 User's Manual U17555EJ3V0UD www..com CHAPTER 13 SERIAL INTERFACES UART60 AND UART61 13.3 Registers Controlling Serial Interfaces UART60 and UART61 Serial interfaces UART60 and UART61 are controlled by the following nine registers. * Asynchronous serial interface operation mode register 6n (ASIM6n) * Asynchronous serial interface reception error status register 6n (ASIS6n) * Asynchronous serial interface transmission status register 6n (ASIF6n) * Clock selection register 6n (CKSR6n) * Baud rate generator control register 6n (BRGC6n) * Asynchronous serial interface control register 6n (ASICL6n) * Input switch control register (ISC) * Port mode register 1 (PM1) * Port register 1 (P1) (1) Asynchronous serial interface operation mode register 6n (ASIM6n) This 8-bit register controls the serial communication operations of serial interface UART60 and UART61. This register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to 01H. Remarks 1. ASIM6n can be refreshed (the same value is written) by software during a communication operation (when bits 7 and 6 (POWER6n, TXE6n) of ASIM6n = 1 or bits 7 and 5 (POWER6n, RXE6n) of ASIM6n = 1). 2. n = 0, 1 User's Manual U17555EJ3V0UD 291 www..com CHAPTER 13 SERIAL INTERFACES UART60 AND UART61 Figure 13-7. Format of Asynchronous Serial Interface Operation Mode Register 60 (ASIM60) (1/2) Address: FF2EH After reset: 01H R/W Symbol ASIM60 <7> POWER60 <6> TXE60 <5> RXE60 4 PS610 3 PS600 2 CL60 1 SL60 0 ISRM60 POWER60 0 Note 1 Enables/disables operation of internal operation clock Disables operation of the internal operation clock (fixes the clock to low level) and asynchronously resets the internal circuit Note 2 . 1 Enables operation of the internal operation clock TXE60 0 1 Enables/disables transmission Disables transmission (synchronously resets the transmission circuit). Enables transmission RXE60 0 1 Enables/disables reception Disables reception (synchronously resets the reception circuit). Enables reception Notes 1. 2. The output of the TXD60 pins goes high level and the input from the RXD60 pins is fixed to the high level when POWER60 = 0 during transmission. Asynchronous serial interface reception error status register 60 (ASIS60), asynchronous serial interface transmission status register 60 (ASIF60), bit 7 (SBRF60) and bit 6 (SBRT60) of asynchronous serial interface control register 60 (ASICL60), and receive buffer register 60 (RXB60) are reset. 292 User's Manual U17555EJ3V0UD www..com CHAPTER 13 SERIAL INTERFACES UART60 AND UART61 Figure 13-7. Format of Asynchronous Serial Interface Operation Mode Register 60 (ASIM60) (2/2) PS610 0 0 1 1 PS600 0 1 0 1 Transmission operation Does not output parity bit. Outputs 0 parity. Outputs odd parity. Outputs even parity. Reception operation Reception without parity Reception as 0 parity Note Judges as odd parity. Judges as even parity. CL60 0 1 Specifies character length of transmit/receive data Character length of data = 7 bits Character length of data = 8 bits SL60 0 1 Number of stop bits = 1 Number of stop bits = 2 Specifies number of stop bits of transmit data ISRM60 0 1 Enables/disables occurrence of reception completion interrupt in case of error "INTSRE60" occurs in case of error (at this time, INTSR60 does not occur). "INTSR60" occurs in case of error (at this time, INTSRE60 does not occur). Note If "reception as 0 parity" is selected, the parity is not judged. Therefore, bit 2 (PE60) of asynchronous serial interface reception error status register 60 (ASIS60) is not set and the error interrupt does not occur. Cautions 1. 2. 3. User's Manual U17555EJ3V0UD 293 www..com CHAPTER 13 SERIAL INTERFACES UART60 AND UART61 Figure 13-8. Format of Asynchronous Serial Interface Operation Mode Register 61 (ASIM61) (1/2) Address: FF2FH After reset: 01H R/W Symbol ASIM61 <7> POWER61 <6> TXE61 <5> RXE61 4 PS611 3 PS601 2 CL61 1 SL61 0 ISRM61 POWER61 0 Note 1 Enables/disables operation of internal operation clock Disables operation of the internal operation clock (fixes the clock to low level) and asynchronously resets the internal circuit Note 2 . 1 Enables operation of the internal operation clock TXE61 0 1 Enables/disables transmission Disables transmission (synchronously resets the transmission circuit). Enables transmission RXE61 0 1 Enables/disables reception Disables reception (synchronously resets the reception circuit). Enables reception Notes 1. 2. The output of the TXD61 pins goes high level and the input from the RXD61 pins is fixed to the high level when POWER61 = 0 during transmission. Asynchronous serial interface reception error status register 61 (ASIS61), asynchronous serial interface transmission status register 61 (ASIF61), bit 7 (SBRF61) and bit 6 (SBRT61) of asynchronous serial interface control register 61 (ASICL61), and receive buffer register 61 (RXB61) are reset. 294 User's Manual U17555EJ3V0UD www..com CHAPTER 13 SERIAL INTERFACES UART60 AND UART61 Figure 13-8. Format of Asynchronous Serial Interface Operation Mode Register 61 (ASIM61) (2/2) PS611 0 0 1 1 PS601 0 1 0 1 Transmission operation Does not output parity bit. Outputs 0 parity. Outputs odd parity. Outputs even parity. Reception operation Reception without parity Reception as 0 parity Note Judges as odd parity. Judges as even parity. CL61 0 1 Specifies character length of transmit/receive data Character length of data = 7 bits Character length of data = 8 bits SL61 0 1 Number of stop bits = 1 Number of stop bits = 2 Specifies number of stop bits of transmit data ISRM61 0 1 Enables/disables occurrence of reception completion interrupt in case of error "INTSRE61" occurs in case of error (at this time, INTSR61 does not occur). "INTSR61" occurs in case of error (at this time, INTSRE61 does not occur). Note If "reception as 0 parity" is selected, the parity is not judged. Therefore, bit 2 (PE61) of asynchronous serial interface reception error status register 61 (ASIS61) is not set and the error interrupt does not occur. Cautions 1. 2. 3. User's Manual U17555EJ3V0UD 295 www..com CHAPTER 13 SERIAL INTERFACES UART60 AND UART61 (2) Asynchronous serial interface reception error status register 6n (ASIS6n) This register indicates an error status on completion of reception by serial interfaces UART60 and UART61. It includes three error flag bits (PE6n, FE6n, OVE6n). This register is read-only by an 8-bit memory manipulation instruction. Reset signal generation, or clearing bit 7 (POWER6n) or bit 5 (RXE6n) of ASIM6n to 0 clears this register to 00H. 00H is read when this register is read. If a reception error occurs, read ASIS6n and then read receive buffer register 6n (RXB6n) to clear the error flag. Figure 13-9. Format of Asynchronous Serial Interface Reception Error Status Register 60 (ASIS60) Address: FF53H After reset: 00H R Symbol ASIS60 7 0 6 0 5 0 4 0 3 0 2 PE60 1 FE60 0 OVE60 PE60 0 1 Status flag indicating parity error If POWER60 = 0 and RXE60 = 0, or if ASIS60 register is read If the parity of transmit data does not match the parity bit on completion of reception FE60 0 1 Status flag indicating framing error If POWER60 = 0 and RXE60 = 0, or if ASIS60 register is read If the stop bit is not detected on completion of reception OVE60 0 1 Status flag indicating overrun error If POWER60 = 0 and RXE60 = 0, or if ASIS60 register is read If receive data is set to the RXB60 register and the next reception operation is completed before the data is read. Cautions 1. The operation of the PE60 bit differs depending on the set values of the PS610 and PS600 bits of asynchronous serial interface operation mode register 60 (ASIM60). 2. The first bit of the receive data is checked as the stop bit, regardless of the number of stop bits. 3. If an overrun error occurs, the next receive data is not written to receive buffer register 60 (RXB60) but discarded. 4. If data is read from ASIS60, a wait cycle is generated. Do not read data from ASIS60 when the CPU is operating on the subsystem clock and the high-speed system clock is stopped. For details, see CHAPTER 30 CAUTIONS FOR WAIT. 296 User's Manual U17555EJ3V0UD www..com CHAPTER 13 SERIAL INTERFACES UART60 AND UART61 Figure 13-10. Format of Asynchronous Serial Interface Reception Error Status Register 61 (ASIS61) Address: FF2FH After reset: 00H R Symbol ASIS61 7 0 6 0 5 0 4 0 3 0 2 PE61 1 FE61 0 OVE61 PE61 0 1 Status flag indicating parity error If POWER61 = 0 and RXE61 = 0, or if ASIS61 register is read If the parity of transmit data does not match the parity bit on completion of reception FE61 0 1 Status flag indicating framing error If POWER61 = 0 and RXE61 = 0, or if ASIS61 register is read If the stop bit is not detected on completion of reception OVE61 0 1 Status flag indicating overrun error If POWER61 = 0 and RXE61 = 0, or if ASIS61 register is read If receive data is set to the RXB61 register and the next reception operation is completed before the data is read. Cautions 1. The operation of the PE61 bit differs depending on the set values of the PS611 and PS601 bits of asynchronous serial interface operation mode register 61 (ASIM61). 2. The first bit of the receive data is checked as the stop bit, regardless of the number of stop bits. 3. If an overrun error occurs, the next receive data is not written to receive buffer register 61 (RXB61) but discarded. 4. If data is read from ASIS61, a wait cycle is generated. Do not read data from ASIS6 when the CPU is operating on the subsystem clock and the high-speed system clock is stopped. For details, see CHAPTER 30 CAUTIONS FOR WAIT. User's Manual U17555EJ3V0UD 297 www..com CHAPTER 13 SERIAL INTERFACES UART60 AND UART61 Address: FF55H After reset: 00H R Symbol ASIF60 7 0 6 0 5 0 4 0 3 0 2 0 1 TXBF60 0 TXSF60 TXBF60 0 1 Transmit buffer data flag If POWER60 = 0 or TXE60 = 0, or if data is transferred to transmit shift register 60 (TXS60) If data is written to transmit buffer register 60 (TXB60) (if data exists in TXB60) TXSF60 0 Transmit shift register data flag If POWER60 = 0 or TXE60 = 0, or if the next data is not transferred from transmit buffer register 60 (TXB60) after completion of transfer 1 If data is transferred from transmit buffer register 60 (TXB60) (if data transmission is in progress) Cautions 1. To transmit data continuously, write the first transmit data (first byte) to the TXB60 register. Be sure to check that the TXBF60 flag is "0". If so, write the next transmit data (second byte) to the TXB60 register. If data is written to the TXB60 register while the TXBF60 flag is "1", the transmit data cannot be guaranteed. 2. To initialize the transmission unit upon completion of continuous transmission, be sure to check that the TXSF60 flag is "0" after generation of the transmission completion interrupt, and then execute initialization. If initialization is executed while the TXSF60 flag is "1", the transmit data cannot be guaranteed. 298 User's Manual U17555EJ3V0UD www..com CHAPTER 13 SERIAL INTERFACES UART60 AND UART61 Figure 13-12. Format of Asynchronous Serial Interface Transmission Status Register 61 (ASIF61) Address: FF38H After reset: 00H R Symbol ASIF61 7 0 6 0 5 0 4 0 3 0 2 0 1 TXBF61 0 TXSF61 TXBF61 0 1 Transmit buffer data flag If POWER61 = 0 or TXE61 = 0, or if data is transferred to transmit shift register 61 (TXS61) If data is written to transmit buffer register 61 (TXB61) (if data exists in TXB61) TXSF61 0 Transmit shift register data flag If POWER61 = 0 or TXE61 = 0, or if the next data is not transferred from transmit buffer register 61 (TXB61) after completion of transfer 1 If data is transferred from transmit buffer register 61 (TXB61) (if data transmission is in progress) Cautions 1. To transmit data continuously, write the first transmit data (first byte) to the TXB61 register. Be sure to check that the TXBF61 flag is "0". If so, write the next transmit data (second byte) to the TXB61 register. If data is written to the TXB61 register while the TXBF61 flag is "1", the transmit data cannot be guaranteed. 2. To initialize the transmission unit upon completion of continuous transmission, be sure to check that the TXSF61 flag is "0" after generation of the transmission completion interrupt, and then execute initialization. If initialization is executed while the TXSF61 flag is "1", the transmit data cannot be guaranteed. User's Manual U17555EJ3V0UD 299 www..com CHAPTER 13 SERIAL INTERFACES UART60 AND UART61 (4) Clock selection register 6n (CKSR6n) This register selects the base clocks of serial interface UART60 and UART61. CKSR6n can be set by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Remark CKSR6n can be refreshed (the same value is written) by software during a communication operation (when bits 7 and 6 (POWER6n, TXE6n) of ASIM6n = 1 or bits 7 and 5 (POWER6n, RXE6n) of ASIM6n = 1). Figure 13-13. Format of Clock Selection Register 60 (CKSR60) Address: FF56H After reset: 00H R/W Symbol CKSR60 7 0 6 0 5 0 4 0 3 TPS630 2 TPS620 1 TPS610 0 TPS600 TPS630 TPS620 TPS610 TPS600 Base clock (fXCLK6) selection fPRS = 4 MHz fPRS = 5 MHz 5 MHz 2.5 MHz 1.25 MHz 625 kHz fPRS = 10 MHz 10 MHz 5 MHz 2.5 MHz 1.25 MHz fPRS = 20 MHz 20 MHz 10 MHz 5 MHz 2.5 MHz 1.25 MHz 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 fPRS fPRS/2 fPRS/2 fPRS/2 fPRS/2 fPRS/2 fPRS/2 fPRS/2 fPRS/2 fPRS/2 fPRS/2 2 4 MHz 2 MHz 1 MHz 500 kHz 250 kHz 125 kHz 62.5 kHz 31.25 kHz 3 4 312.5 kHz 625 kHz 5 156.25 kHz 312.5 kHz 625 kHz 78.13 kHz 156.25 kHz 312.5 kHz 39.06 kHz 78.13 kHz 156.25 kHz 6 7 8 15.625 kHz 19.53 kHz 39.06 kHz 78.13 kHz 7.813 kHz 9.77 kHz 3.906 kHz 4.88 kHz Note 9 19.53 kHz 39.06 kHz 9.77 kHz 19.53 kHz 10 TM50 output Other than above Setting prohibited Note Note the following points when selecting the TM50 output as the base clock. * Mode in which the count clock is cleared and started upon a match of TM50 and CR50 (TMC506 = 0) Start the operation of 8-bit timer/event counter 50 first and then enable the timer F/F inversion operation (TMC501 = 1). * PWM mode (TMC506 = 1) Start the operation of 8-bit timer/event counter 50 first and then set the count clock to make the duty = 50%. It is not necessary to enable the TO50 pin as a timer output pin in any mode. Caution Make sure POWER60 = 0 when rewriting TPS630 to TPS600. Remarks 1. fPRS: Peripheral hardware clock frequency 2. TMC506: Bit 6 of 8-bit timer mode control register 50 (TMC50) TMC501: Bit 1 of TMC50 300 User's Manual U17555EJ3V0UD www..com CHAPTER 13 SERIAL INTERFACES UART60 AND UART61 Figure 13-14. Format of Clock Selection Register 61 (CKSR61) Address: FF39H After reset: 00H R/W Symbol CKSR61 7 0 6 0 5 0 4 0 3 TPS631 2 TPS621 1 TPS611 0 TPS601 TPS631 TPS621 TPS611 TPS601 Base clock (fXCLK6) selection fPRS = 4 MHz fPRS = 5 MHz 5 MHz 2.5 MHz 1.25 MHz 625 kHz fPRS = 10 MHz 10 MHz 5 MHz 2.5 MHz 1.25 MHz fPRS = 20 MHz 20 MHz 10 MHz 5 MHz 2.5 MHz 1.25 MHz 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 fPRS fPRS/2 fPRS/2 fPRS/2 fPRS/2 fPRS/2 fPRS/2 fPRS/2 fPRS/2 fPRS/2 fPRS/2 2 4 MHz 2 MHz 1 MHz 500 kHz 250 kHz 125 kHz 62.5 kHz 31.25 kHz 3 4 312.5 kHz 625 kHz 5 156.25 kHz 312.5 kHz 625 kHz 78.13 kHz 156.25 kHz 312.5 kHz 39.06 kHz 78.13 kHz 156.25 kHz 6 7 8 15.625 kHz 19.53 kHz 39.06 kHz 78.13 kHz 7.813 kHz 9.77 kHz 3.906 kHz 4.88 kHz Note 9 19.53 kHz 39.06 kHz 9.77 kHz 19.53 kHz 10 TM50 output Other than above Setting prohibited Note Note the following points when selecting the TM50 output as the base clock. * Mode in which the count clock is cleared and started upon a match of TM50 and CR50 (TMC506 = 0) Start the operation of 8-bit timer/event counter 50 first and then enable the timer F/F inversion operation (TMC501 = 1). * PWM mode (TMC506 = 1) Start the operation of 8-bit timer/event counter 50 first and then set the count clock to make the duty = 50%. It is not necessary to enable the TO50 pin as a timer output pin in any mode. Caution Make sure POWER61 = 0 when rewriting TPS631 to TPS601. Remarks 1. fPRS: Peripheral hardware clock frequency 2. TMC506: Bit 6 of 8-bit timer mode control register 50 (TMC50) TMC501: Bit 1 of TMC50 User's Manual U17555EJ3V0UD 301 www..com CHAPTER 13 SERIAL INTERFACES UART60 AND UART61 (5) Baud rate generator control register 6n (BRGC6n) This register sets the division value of the 8-bit counters of serial interface UART60 and UART61. BRGC6n can be set by an 8-bit memory manipulation instruction. Reset signal generation sets this register to FFH. Remark BRGC6n can be refreshed (the same value is written) by software during a communication operation (when bits 7 and 6 (POWER6n, TXE6n) of ASIM6n = 1 or bits 7 and 5 (POWER6n, RXE6n) of ASIM6n = 1). Figure 13-15. Format of Baud Rate Generator Control Register 60 (BRGC60) Address: FF57H After reset: FFH R/W Symbol BRGC60 7 6 5 4 3 2 1 0 MDL670 MDL660 MDL650 MDL640 MDL630 MDL620 MDL610 MDL600 MDL670 MDL660 MDL650 MDL640 MDL630 MDL620 MDL610 MDL600 x 0 0 1 * * * * * 0 0 1 1 x 0 1 0 * * * * * 0 1 0 1 k x 4 5 6 * * * * * 252 253 254 255 Output clock selection of 8-bit counter 0 0 0 0 0 * * * * * 1 1 1 1 0 0 0 0 * * * * * 1 1 1 1 0 0 0 0 * * * * * 1 1 1 1 0 0 0 0 * * * * * 1 1 1 1 0 1 1 1 * * * * * 1 1 1 1 Setting prohibited fXCLK6/4 fXCLK6/5 fXCLK6/6 * * * * * fXCLK6/252 fXCLK6/253 fXCLK6/254 fXCLK6/255 0 0 0 * * * * * 1 1 1 1 Cautions 1. Make sure that bit 6 (TXE60) and bit 5 (RXE60) of the ASIM6n register = 0 when rewriting the MDL670 to MDL600 bits. 2. The baud rate is the output clock of the 8-bit counter divided by 2. Remarks 1. fXCLK6: Frequency of base clock selected by the TPS630 to TPS600 bits of CKSR60 register 302 User's Manual U17555EJ3V0UD www..com CHAPTER 13 SERIAL INTERFACES UART60 AND UART61 Figure 13-16. Format of Baud Rate Generator Control Register 61 (BRGC61) Address: FF3EH After reset: FFH R/W Symbol BRGC61 7 6 5 4 3 2 1 0 MDL671 MDL661 MDL651 MDL641 MDL631 MDL621 MDL611 MDL601 MDL671 MDL661 MDL651 MDL641 MDL631 MDL621 MDL611 MDL601 x 0 0 1 * * * * * 0 0 1 1 x 0 1 0 * * * * * 0 1 0 1 k x 4 5 6 * * * * * 252 253 254 255 Output clock selection of 8-bit counter 0 0 0 0 0 * * * * * 1 1 1 1 0 0 0 0 * * * * * 1 1 1 1 0 0 0 0 * * * * * 1 1 1 1 0 0 0 0 * * * * * 1 1 1 1 0 1 1 1 * * * * * 1 1 1 1 Setting prohibited fXCLK6/4 fXCLK6/5 fXCLK6/6 * * * * * fXCLK6/252 fXCLK6/253 fXCLK6/254 fXCLK6/255 0 0 0 * * * * * 1 1 1 1 Cautions 1. Make sure that bit 6 (TXE61) and bit 5 (RXE61) of the ASIM61 register = 0 when rewriting the MDL671 to MDL601 bits. 2. The baud rate is the output clock of the 8-bit counter divided by 2. Remarks 1. fXCLK6: Frequency of base clock selected by the TPS631 to TPS601 bits of CKSR61 register User's Manual U17555EJ3V0UD 303 www..com CHAPTER 13 SERIAL INTERFACES UART60 AND UART61 (6) Asynchronous serial interface control register 6n (ASICL6n) This register controls the serial communication operations of serial interface UART60 and UART61. ASICL6n can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to 16H. Address: FF58H After reset: 16H R/W Symbol ASICL60 <7> SBRF60 <6> SBRT60 Note 5 SBTT60 4 SBL620 3 SBL610 2 SBL600 1 DIR60 0 TXDLV60 SBRF60 0 1 SBF reception status flag If POWER60 = 0 and RXE60 = 0 or if SBF reception has been completed correctly SBF reception in progress SBRT60 0 1 SBF reception trigger SBF reception trigger - SBTT60 0 1 SBF transmission trigger SBF transmission trigger - Note Bit 7 is read-only. 304 User's Manual U17555EJ3V0UD www..com CHAPTER 13 SERIAL INTERFACES UART60 AND UART61 Figure 13-17. Format of Asynchronous Serial Interface Control Register 60 (ASICL60) (2/2) SBL620 1 1 1 0 0 0 0 1 SBL610 0 1 1 0 0 1 1 0 SBL600 1 0 1 0 1 0 1 0 SBF transmission output width control SBF is output with 13-bit length. SBF is output with 14-bit length. SBF is output with 15-bit length. SBF is output with 16-bit length. SBF is output with 17-bit length. SBF is output with 18-bit length. SBF is output with 19-bit length. SBF is output with 20-bit length. DIR60 0 1 MSB LSB First-bit specification TXDLV60 0 1 Normal output of TXD60 Inverted output of TXD60 Enables/disables inverting TXD6n output Cautions 1. In the case of an SBF reception error, the mode returns to the SBF reception mode. The status of the SBRF60 flag is held (1). 2. Before setting the SBRT60 bit, make sure that bit 7 (POWER60) and bit 5 (RXE60) of ASIM60 = 1. After setting the SBRT60 bit to 1, do not clear it to 0 before SBF reception is completed (before an interrupt request signal is generated). 3. The read value of the SBRT60 bit is always 0. SBRT60 is automatically cleared to 0 after SBF reception has been correctly completed. 4. Before setting the SBTT60 bit to 1, make sure that bit 7 (POWER60) and bit 6 (TXE60) of ASIM60 = 1. After setting the SBTT60 bit to 1, do not clear it to 0 before SBF transmission is completed (before an interrupt request signal is generated). 5. The read value of the SBTT60 bit is always 0. SBTT60 is automatically cleared to 0 at the end of SBF transmission. 6. Do not set the SBRT60 bit to 1 during reception, and do not set the SBTT60 bit to 1 during transmission. 7 Before rewriting the DIR60 and TXDLV60 bits, clear the TXE60 and RXE60 bits to 0. User's Manual U17555EJ3V0UD 305 www..com CHAPTER 13 SERIAL INTERFACES UART60 AND UART61 Figure 13-18. Format of Asynchronous Serial Interface Control Register 61 (ASICL61) (1/2) Address: FF3FH After reset: 16H R/W Symbol ASICL61 <7> SBRF61 <6> SBRT61 Note 5 SBTT61 4 SBL621 3 SBL611 2 SBL601 1 DIR61 0 TXDLV61 SBRF61 0 1 SBF reception status flag If POWER61 = 0 and RXE61 = 0 or if SBF reception has been completed correctly SBF reception in progress SBRT61 0 1 SBF reception trigger SBF reception trigger - SBTT61 0 1 SBF transmission trigger SBF transmission trigger - Note Bit 7 is read-only. 306 User's Manual U17555EJ3V0UD www..com CHAPTER 13 SERIAL INTERFACES UART60 AND UART61 Figure 13-18. Format of Asynchronous Serial Interface Control Register 61 (ASICL61) (2/2) SBL621 1 1 1 0 0 0 0 1 SBL611 0 1 1 0 0 1 1 0 SBL601 1 0 1 0 1 0 1 0 SBF transmission output width control SBF is output with 13-bit length. SBF is output with 14-bit length. SBF is output with 15-bit length. SBF is output with 16-bit length. SBF is output with 17-bit length. SBF is output with 18-bit length. SBF is output with 19-bit length. SBF is output with 20-bit length. DIR61 0 1 MSB LSB First-bit specification TXDLV61 0 1 Normal output of TXD6n Inverted output of TXD6n Enables/disables inverting TXD6n output Cautions 1. In the case of an SBF reception error, the mode returns to the SBF reception mode. The status of the SBRF61 flag is held (1). 2. Before setting the SBRT61 bit, make sure that bit 7 (POWER61) and bit 5 (RXE61) of ASIM61 = 1. After setting the SBRT61 bit to 1, do not clear it to 0 before SBF reception is completed (before an interrupt request signal is generated). 3. The read value of the SBRT61 bit is always 0. SBRT61 is automatically cleared to 0 after SBF reception has been correctly completed. 4. Before setting the SBTT61 bit to 1, make sure that bit 7 (POWER61) and bit 6 (TXE61) of ASIM61 = 1. After setting the SBTT61 bit to 1, do not clear it to 0 before SBF transmission is completed (before an interrupt request signal is generated). 5. The read value of the SBTT61 bit is always 0. SBTT61 is automatically cleared to 0 at the end of SBF transmission. 6. Do not set the SBRT61 bit to 1 during reception, and do not set the SBTT61 bit to 1 during transmission. 7. Before rewriting the DIR61 and TXDLV61 bits, clear the TXE61 and RXE61 bits to 0. User's Manual U17555EJ3V0UD 307 www..com CHAPTER 13 SERIAL INTERFACES UART60 AND UART61 (7) Input switch control register (ISC) The input switch control register (ISC) is used to receive a status signal transmitted from the master during LIN (Local Interconnect Network) reception. The input source is switched by setting ISC. This register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 13-19. Format of Input Switch Control Register (ISC) Address: FF4FH Symbol ISC After reset: 00H 7 ISC7 6 0 R/W 5 0 4 ISC4 3 ISC3 2 1 Note 1 ISC1 0 ISC0 ISC7 0 1 INTWTI INTDMU Interrupt source selection ISC4 0 1 INTP1 (P30) RxD61(P11) INTP1 input source selection ISC3 0 1 INTP0 (P120) RxD60 (P14) INTP0 input source selection ISC1 0 1 TI010 (P01) RxD60 (P14) TI010 input source selection ISC0 0 1 TI000 (P00) TSOUT TI000 input source selection Note Be sure to set bit 2 of ISC to 1. 308 User's Manual U17555EJ3V0UD www..com CHAPTER 13 SERIAL INTERFACES UART60 AND UART61 (8) Port mode register 1 (PM1) This register sets port 1 input/output in 1-bit units. When using the P13/TxD60 and P10/SCK10/TxD61 pins for serial interface data output, clear PM13 and PM10 to 0 and set the output latch of P13 and P10 to 1. When using the P14/RxD60 and P11/SI10/RxD61 in for serial interface data input, set PM14 and PM11 to 1. The output latch of P14 and P11 at this time may be 0 or 1. PM1 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to FFH. Figure 13-20. Format of Port Mode Register 1 (PM1) Address: FF21H Symbol PM1 7 PM17 After reset: FFH 6 PM16 R/W 5 PM15 4 PM14 3 PM13 2 PM12 1 PM11 0 PM10 PM1n 0 1 P1n pin I/O mode selection (n = 0 to 7) Output mode (output buffer on) Input mode (output buffer off) User's Manual U17555EJ3V0UD 309 www..com CHAPTER 13 SERIAL INTERFACES UART60 AND UART61 13.4 Operations of Serial Interface UART60 and UART61 Serial interfaces UART60 and UART61 have the following two modes. * Operation stop mode * Asynchronous serial interface (UART) mode 13.4.1 Operation stop mode In this mode, serial communication cannot be executed; therefore, the power consumption can be reduced. In addition, the pins can be used as ordinary port pins in this mode. To set the operation stop mode, clear bits 7, 6, and 5 (POWER6n, TXE6n, and RXE6n) of ASIM6n to 0. (1) Register used The operation stop mode is set by asynchronous serial interface operation mode register 6n (ASIM6n). ASIM6n can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to 01H. Address: FF50H After reset: 01H R/W Symbol ASIM6n <7> POWER6n <6> TXE6n <5> RXE6n 4 PS61n 3 PS60n 2 CL6n 1 SL6n 0 ISRM6n POWER6n 0 Note 1 Enables/disables operation of internal operation clock Disables operation of the internal operation clock (fixes the clock to low level) and asynchronously resets the internal circuit Note 2 . TXE6n 0 Enables/disables transmission Disables transmission operation (synchronously resets the transmission circuit). RXE6n 0 Enables/disables reception Disables reception (synchronously resets the reception circuit). Notes 1. 2. The output of the TXD6n pins goes high and the input from the RXD6n pins is fixed to high level when POWER6n = 0. Asynchronous serial interface reception error status register 6n (ASIS6n), asynchronous serial interface transmission status register 6n (ASIF6n), bit 7 (SBRF6n) and bit 6 (SBRT6n) of asynchronous serial interface control register 6n (ASICL6n), and receive buffer register 6n (RXB6n) are reset. Caution Clear POWER6n to 0 after clearing TXE6n and RXE6n to 0 to stop the operation. To start the communication, set POWER6n to 1, and then set TXE6n and RXE6n to 1. Remarks 1. 2. To use the RxD60/P14, RxD61/P11/SI10, TxD60/P13 and TxD61/P10/SCK10 pins as generalpurpose port pins, see CHAPTER 4 PORT FUNCTIONS. n = 0, 1 310 User's Manual U17555EJ3V0UD www..com CHAPTER 13 SERIAL INTERFACES UART60 AND UART61 13.4.2 Asynchronous serial interface (UART) mode In this mode, data of 1 byte is transmitted/received following a start bit, and a full-duplex operation can be performed. A dedicated UART baud rate generator is incorporated, so that communication can be executed at a wide range of baud rates. (1) Registers used * Asynchronous serial interface operation mode register 6n (ASIM6n) * Asynchronous serial interface reception error status register 6n (ASIS6n) * Asynchronous serial interface transmission status register 6n (ASIF6n) * Clock selection register 6n (CKSR6n) * Baud rate generator control register 6n (BRGC6n) * Asynchronous serial interface control register 6n (ASICL6n) * Input switch control register (ISC) * Port mode register 1 (PM1) * Port register 1 (P1) The basic procedure of setting an operation in the UART mode is as follows. <1> Set the CKSR6n register (see Figure 13-13, 13-14). <2> Set the BRGC6n register (see Figure 13-15, 13-16). <3> Set bits 0 to 4 (ISRM6n, SL6n, CL6n, PS60n, PS61n) of the ASIM6n register (see Figure 13-7, 13-8). <4> Set bits 0 and 1 (TXDLV6n, DIR6n) of the ASICL6n register (see Figure 13-17, 13-18). <5> Set bit 7 (POWER6n) of the ASIM6n register to 1. <6> Set bit 6 (TXE6n) of the ASIM6n register to 1. Transmission is enabled. Set bit 5 (RXE6n) of the ASIM6n register to 1. Reception is enabled. <7> Write data to transmit buffer register 6n (TXB6n). Data transmission is started. Caution Take relationship with the other party of communication when setting the port mode register and port register. Remark n = 0, 1 User's Manual U17555EJ3V0UD 311 www..com CHAPTER 13 SERIAL INTERFACES UART60 AND UART61 The relationship between the register settings and pins is shown below. Table 13-2. Relationship Between Register Settings and Pins (a) UART60 POWER6n TXE6n RXE6n PM13 P13 PM14 P14 UART60 Operation 0 1 0 0 1 1 0 1 0 1 x x Note Pin Function TxD60/P13 P13 P13 TxD60 TxD60 RxD60/P14 P14 RxD60 P14 RxD60 x x Note x Note x Note Stop Reception Transmission Transmission/ reception Note Note 1 x Note x x Note 0 0 1 1 1 x (b) UART61 POWER6n TXE6n RXE6n PM10 P10 PM11 P11 UART61 Operation 0 1 0 0 1 1 0 1 0 1 x x Note Pin Function TxD61/P10/SCK61 P10 P10 TxD61 TxD61 RxD61/P11/SI10 P11 RxD61 P11 RxD61 x x Note x Note x Note Stop Reception Transmission Transmission/ reception Note Note 1 x Note x x Note 0 0 1 1 1 x Note Can be set as port function. x: TXE6n: RXE6n: PM1x: P1x: n = 0, 1 don't care Bit 6 of ASIM6n Bit 5 of ASIM6n Port mode register Port output latch Remark POWER6n: Bit 7 of asynchronous serial interface operation mode register 6n (ASIM6n) 312 User's Manual U17555EJ3V0UD www..com CHAPTER 13 SERIAL INTERFACES UART60 AND UART61 (2) Communication operation (a) Format and waveform example of normal transmit/receive data Figures 13-21 and 13-22 show the format and waveform example of the normal transmit/receive data. Figure 13-21. Format of Normal UART Transmit/Receive Data 1. LSB-first transmission/reception 1 data frame Start bit D0 D1 D2 D3 D4 D5 D6 D7 Parity bit Stop bit Character bits 2. MSB-first transmission/reception 1 data frame Start bit D7 D6 D5 D4 D3 D2 D1 D0 Parity bit Stop bit Character bits One data frame consists of the following bits. * Start bit ... 1 bit * Character bits ... 7 or 8 bits * Parity bit ... Even parity, odd parity, 0 parity, or no parity * Stop bit ... 1 or 2 bits The character bit length, parity, and stop bit length in one data frame are specified by asynchronous serial interface operation mode register 6n (ASIM6n). Whether data is communicated with the LSB or MSB first is specified by bit 1 (DIR6) of asynchronous serial interface control register 6n (ASICL6n). Whether the TXD6n pins outputs normal or inverted data is specified by bit 0 (TXDLV6) of ASICL6n. Remark n = 0, 1 User's Manual U17555EJ3V0UD 313 www..com CHAPTER 13 SERIAL INTERFACES UART60 AND UART61 Figure 13-22. Example of Normal UART Transmit/Receive Data Waveform 1. Data length: 8 bits, LSB first, Parity: Even parity, Stop bit: 1 bit, Communication data: 55H 1 data frame Start D0 D1 D2 D3 D4 D5 D6 D7 Parity Stop 2. Data length: 8 bits, MSB first, Parity: Even parity, Stop bit: 1 bit, Communication data: 55H 1 data frame Start D7 D6 D5 D4 D3 D2 D1 D0 Parity Stop 3. Data length: 8 bits, MSB first, Parity: Even parity, Stop bit: 1 bit, Communication data: 55H, TXD6n pin inverted output 1 data frame Start D7 D6 D5 D4 D3 D2 D1 D0 Parity Stop 4. Data length: 7 bits, LSB first, Parity: Odd parity, Stop bit: 2 bits, Communication data: 36H 1 data frame Start D0 D1 D2 D3 D4 D5 D6 Parity Stop Stop 5. Data length: 8 bits, LSB first, Parity: None, Stop bit: 1 bit, Communication data: 87H 1 data frame Start D0 D1 D2 D3 D4 D5 D6 D7 Stop Remark n = 0, 1 314 User's Manual U17555EJ3V0UD www..com CHAPTER 13 SERIAL INTERFACES UART60 AND UART61 (b) Parity types and operation The parity bit is used to detect a bit error in communication data. Usually, the same type of parity bit is used on both the transmission and reception sides. With even parity and odd parity, a 1-bit (odd number) error can be detected. With zero parity and no parity, an error cannot be detected. Caution Fix the PS61n and PS60n bits to 0 when the device is used in LIN communication operation. (i) Even parity * Transmission Transmit data, including the parity bit, is controlled so that the number of bits that are "1" is even. The value of the parity bit is as follows. If transmit data has an odd number of bits that are "1": 1 If transmit data has an even number of bits that are "1": 0 * Reception The number of bits that are "1" in the receive data, including the parity bit, is counted. If it is odd, a parity error occurs. (ii) Odd parity * Transmission Unlike even parity, transmit data, including the parity bit, is controlled so that the number of bits that are "1" is odd. If transmit data has an odd number of bits that are "1": 0 If transmit data has an even number of bits that are "1": 1 * Reception The number of bits that are "1" in the receive data, including the parity bit, is counted. If it is even, a parity error occurs. (iii) 0 parity The parity bit is cleared to 0 when data is transmitted, regardless of the transmit data. The parity bit is not detected when the data is received. Therefore, a parity error does not occur regardless of whether the parity bit is "0" or "1". (iv) No parity No parity bit is appended to the transmit data. Reception is performed assuming that there is no parity bit when data is received. Because there is no parity bit, a parity error does not occur. Remark n = 0, 1 User's Manual U17555EJ3V0UD 315 www..com CHAPTER 13 SERIAL INTERFACES UART60 AND UART61 (c) Normal transmission TXD6n (output) Start D0 D1 D2 D6 D7 Parity Stop INTST6n 2. Stop bit length: 2 TXD6n (output) Start D0 D1 D2 D6 D7 Parity Stop INTST6n Remark n = 0, 1 316 User's Manual U17555EJ3V0UD www..com CHAPTER 13 SERIAL INTERFACES UART60 AND UART61 (d) Continuous transmission The next transmit data can be written to transmit buffer register 6n (TXB6n) as soon as transmit shift register 6 (TXS6n) has started its shift operation. Consequently, even while the INTST6n interrupt is being serviced after transmission of one data frame, data can be continuously transmitted and an efficient communication rate can be realized. In addition, the TXB6n register can be efficiently written twice (2 bytes) without having to wait for the transmission time of one data frame, by reading bit 0 (TXSF6n) of asynchronous serial interface transmission status register 6n (ASIF6n) when the transmission completion interrupt has occurred. To transmit data continuously, be sure to reference the ASIF6n register to check the transmission status and whether the TXB6n register can be written, and then write the data. Cautions 1. The TXBF6n and TXSF6n flags of the ASIF6n register change from "10" to "11", and to "01" during continuous transmission. To check the status, therefore, do not use a combination of the TXBF6n and TXSF6n flags for judgment. Read only the TXBF6n flag when executing continuous transmission. 2. When the device is used in LIN communication operation, the continuous transmission function cannot be used. Make sure that asynchronous serial interface transmission status register 6n (ASIF6n) is 00H before writing transmit data to transmit buffer register 6n (TXB6n). TXBF6n 0 1 Writing enabled Writing disabled Writing to TXB6 Register Caution To transmit data continuously, write the first transmit data (first byte) to the TXB6n register. Be sure to check that the TXBF6n flag is "0". If so, write the next transmit data (second byte) to the TXB6n register. If data is written to the TXB6n register while the TXBF6n flag is "1", the transmit data cannot be guaranteed. The communication status can be checked using the TXSF6n flag. TXSF6n 0 1 Transmission is completed. Transmission is in progress. Transmission Status Cautions 1. To initialize the transmission unit upon completion of continuous transmission, be sure to check that the TXSF6n flag is "0" after generation of the transmission completion interrupt, and then execute initialization. If initialization is executed while the TXSF6n flag is "1", the transmit data cannot be guaranteed. 2. During continuous transmission, an overrun error may occur, which means that the next transmission was completed before execution of TXSF6n interrupt servicing after transmission of one data frame. An overrun error can be detected by developing a program that can count the number of transmit data and by referencing the TXSF6n flag. Remark n = 0, 1 User's Manual U17555EJ3V0UD 317 www..com CHAPTER 13 SERIAL INTERFACES UART60 AND UART61 Figure 13-24 shows an example of the continuous transmission processing flow. Figure 13-24. Example of Continuous Transmission Processing Flow Set registers. Write TXB6n. Transfer executed necessary number of times? No Yes Read ASIF6n TXBF6n = 0? Yes No Write TXB6n. Transmission completion interrupt occurs? Yes No Transfer executed necessary number of times? No Yes Read ASIF6n TXSF6n = 0? Yes Yes Completion of transmission processing No Remark TXB6n: ASIF6n: Transmit buffer register 6n Asynchronous serial interface transmission status register 6n TXBF6n: Bit 1 of ASIF6n (transmit buffer data flag) 318 User's Manual U17555EJ3V0UD www..com CHAPTER 13 SERIAL INTERFACES UART60 AND UART61 Figure 13-25 shows the timing of starting continuous transmission, and Figure 13-25 shows the timing of ending continuous transmission. TXD6n INTST6n Figure 13-25. Timing of Starting Continuous Transmission Start Data (1) Parity Stop Start Data (2) Parity Stop Start TXB6n FF Data (1) Data (2) Data (3) TXS6n TXBF6n TXSF6n FF Data (1) Data (2) Data (3) Note Note When ASIF6n is read, there is a period in which TXBF6n and TXSF6n = 1, 1. Therefore, judge whether writing is enabled using only the TXBF6n bit. Remark TXD6n: TXB6n: TXS6n: ASIF6n: TxD6n pins (output) Transmit buffer register 6n Transmit shift register 6n Asynchronous serial interface transmission status register 6n INTST6n: Interrupt request signal TXBF6n: Bit 1 of ASIF6n TXSF6n: Bit 0 of ASIF6n n = 0, 1 User's Manual U17555EJ3V0UD 319 www..com CHAPTER 13 SERIAL INTERFACES UART60 AND UART61 Figure 13-26. Timing of Ending Continuous Transmission TXD6n INTST6n Stop Start Data (n - 1) Parity Stop Start Data (n) Parity Stop TXB6n Data (n - 1) Data (n) TXS6n Data (n - 1) Data (n) FF TXBF6n TXSF6n POWER6n or TXE6n Remark TXD6n: INTST6n: TXB6n: TXS6n: ASIF6n: TXBF6n: TXD6n pins (output) Interrupt request signal Transmit buffer register 6n Transmit shift register 6n Asynchronous serial interface transmission status register 6n Bit 1 of ASIF6n Bit 0 of ASIF6n Bit 6 of asynchronous serial interface operation mode register (ASIM6n) TXSF6n: TXE6n: n = 0, 1 POWER6n: Bit 7 of asynchronous serial interface operation mode register (ASIM6n) 320 User's Manual U17555EJ3V0UD www..com CHAPTER 13 SERIAL INTERFACES UART60 AND UART61 (e) Normal reception Reception is enabled and the RXD6n pins input is sampled when bit 7 (POWER6n) of asynchronous serial interface operation mode register 6n (ASIM6n) is set to 1 and then bit 5 (RXE6n) of ASIM6n is set to 1. The 8-bit counter of the baud rate generator starts counting when the falling edge of the RXD6n pins input is detected. When the set value of baud rate generator control register 6n (BRGC6n) has been counted, the RXD6n pins input is sampled again ( recognized as a start bit. When the start bit is detected, reception is started, and serial data is sequentially stored in the receive shift register (RXS6n) at the set baud rate. When the stop bit has been received, the reception completion interrupt (INTSR6n) is generated and the data of RXS6n is written to receive buffer register 6n (RXB6n). If an overrun error (OVE6n) occurs, however, the receive data is not written to RXB6n. Even if a parity error (PE6n) occurs while reception is in progress, reception continues to the reception position of the stop bit, and an error interrupt (INTSR6n/INTSRE6n) is generated on completion of reception. Figure 13-27. Reception Completion Interrupt Request Timing in Figure 13-27). If the RXD6n pins are low level at this time, it is RXD6n (input) Start D0 D1 D2 D3 D4 D5 D6 D7 Parity Stop INTSR6n RXB6n Cautions 1. If a reception error occurs, read ASIS6n and then RXB6n to clear the error flag. Otherwise, an overrun error will occur when the next data is received, and the reception error status will persist. 2. Reception is always performed with the "number of stop bits = 1". The second stop bit is ignored. 3. Be sure to read asynchronous serial interface reception error status register 6n (ASIS6n) before reading RXB6n. Remark n = 0, 1 User's Manual U17555EJ3V0UD 321 www..com CHAPTER 13 SERIAL INTERFACES UART60 AND UART61 (f) Reception error Three types of errors may occur during reception: a parity error, framing error, or overrun error. If the error flag of asynchronous serial interface reception error status register 6n (ASIS6n) is set as a result of data reception, a reception error interrupt request (INTSR6n/INTSRE6n) is generated. Which error has occurred during reception can be identified by reading the contents of ASIS6n in the reception error interrupt servicing (INTSR6n/INTSRE6n) (see Figure 13-9, 13-10). The contents of ASIS6n are cleared to 0 when ASIS6n is read. Table 13-3. Cause of Reception Error Reception Error Parity error Framing error Overrun error Cause The parity specified for transmission does not match the parity of the receive data. Stop bit is not detected. Reception of the next data is completed before data is read from receive buffer register 6n (RXB6n). The error interrupt can be separated into reception completion interrupt (INTSR6n) and error interrupt (INTSRE6n) by clearing bit 0 (ISRM6n) of asynchronous serial interface operation mode register 6n (ASIM6n) to 0. Figure 13-28. Reception Error Interrupt 1. If ISRM6n is cleared to 0 (reception completion interrupt (INTSR6n) and error interrupt (INTSRE6n) are separated) (a) No error during reception INTSR6n (b) Error during reception INTSR6n INTSRE6n INTSRE6n 2. If ISRM6n is set to 1 (error interrupt is included in INTSR6n) (a) No error during reception (b) Error during reception INTSR6n INTSRE6n INTSR6n INTSRE6n Remark n = 0, 1 322 User's Manual U17555EJ3V0UD www..com CHAPTER 13 SERIAL INTERFACES UART60 AND UART61 (g) Noise filter of receive data The RXD6n signal's is sampled with the base clock output by the prescaler block. If two sampled values are the same, the output of the match detector changes, and the data is sampled as input data. Because the circuit is configured as shown in Figure 13-29, the internal processing of the reception operation is delayed by two clocks from the external signal status. Figure 13-29. Noise Filter Circuit Base clock RXD60/P14 RxD61/P11SI10 In Q Internal signal A In Q Internal signal B Match detector LD_EN User's Manual U17555EJ3V0UD 323 www..com CHAPTER 13 SERIAL INTERFACES UART60 AND UART61 (h) SBF transmission When the device is used in LIN communication operation, the SBF (Synchronous Break Field) transmission control function is used for transmission. For the transmission operation of LIN, see Figure 13-1 LIN Transmission Operation. TXD6n 1 2 3 4 5 6 7 8 9 10 11 12 13 Stop INTST6n SBTT6n TXD6n pins (output) Remark TXD6n: INTST6n: Transmission completion interrupt request SBTT6n: Bit 5 of asynchronous serial interface control register 6n (ASICL6n) n = 0, 1 324 User's Manual U17555EJ3V0UD www..com CHAPTER 13 SERIAL INTERFACES UART60 AND UART61 (i) SBF reception When the device is incorporated in LIN, the SBF (Synchronous Break Field) reception control function is used for reception. For the reception operation of LIN, see Figure 13-2 LIN Reception Operation. Reception is enabled when bit 7 (POWER6n) of asynchronous serial interface operation mode register 6n (ASIM6n) is set to 1 and then bit 5 (RXE6n) of ASIM6n is set to 1. SBF reception is enabled when bit 6 (SBRT6n) of asynchronous serial interface control register 6n (ASICL6n) is set to 1. In the SBF reception enabled status, the RXD6n pins are sampled and the start bit is detected in the same manner as the normal reception enable status. When the start bit has been detected, reception is started, and serial data is sequentially stored in the receive shift register 6n (RXS6n) at the set baud rate. When the stop bit is received and if the width of SBF is 11 bits or more, a reception completion interrupt request (INTSR6n) is generated as normal processing. At this time, the SBRF6n and SBRT6n bits are automatically cleared, and SBF reception ends. Detection of errors, such as OVE6n, PE6n, and FE6n (bits 0 to 2 of asynchronous serial interface reception error status register 6n (ASIS6n)) is suppressed, and error detection processing of UART communication is not performed. In addition, data transfer between receive shift register 6n (RXS6n) and receive buffer register 6n (RXB6n) is not performed, and the reset value of FFH is retained. If the width of SBF is 10 bits or less, an interrupt does not occur as error processing after the stop bit has been received, and the SBF reception mode is restored. In this case, the SBRF6n and SBRT6n bits are not cleared. Figure 13-31. SBF Reception 1. Normal SBF reception (stop bit is detected with a width of more than 10.5 bits) 1 2 3 4 5 6 7 8 9 10 11 RXD6n SBRT6n /SBRF6n INTSR6n 2. SBF reception error (stop bit is detected with a width of 10.5 bits or less) RXD6n 1 2 3 4 5 6 7 8 9 10 SBRT6n /SBRF6n INTSR6n "0" Remark RXD6n: RXD6n pins (input) SBRT6n: Bit 6 of asynchronous serial interface control register 6n (ASICL6n) SBRF6n: Bit 7 of ASICL6n INTSR6n: Reception completion interrupt request n = 0, 1 User's Manual U17555EJ3V0UD 325 www..com CHAPTER 13 SERIAL INTERFACES UART60 AND UART61 13.4.3 Dedicated baud rate generator The dedicated baud rate generator consists of a source clock selector and an 8-bit programmable counter, and generates a serial clock for transmission/reception of UART60 and UART61. Separate 8-bit counters are provided for transmission and reception. (1) Configuration of baud rate generator * Base clock The clock selected by bits 3 to 0 (TPS63n to TPS60n) of clock selection register 6n (CKSR6n) is supplied to each module when bit 7 (POWER6n) of asynchronous serial interface operation mode register 6n (ASIM6n) is 1. This clock is called the base clock and its frequency is called fXCLK6. The base clock is fixed to low level when POWER6n = 0. * Transmission counter This counter stops operation, cleared to 0, when bit 7 (POWER6n) or bit 6 (TXE6n) of asynchronous serial interface operation mode register 6n (ASIM6n) is 0. It starts counting when POWER6n = 1 and TXE6n = 1. The counter is cleared to 0 when the first data transmitted is written to transmit buffer register 6n (TXB6n). If data are continuously transmitted, the counter is cleared to 0 again when one frame of data has been completely transmitted. If there is no data to be transmitted next, the counter is not cleared to 0 and continues counting until POWER6n or TXE6n is cleared to 0. * Reception counter This counter stops operation, cleared to 0, when bit 7 (POWER6n) or bit 5 (RXE6n) of asynchronous serial interface operation mode register 6n (ASIM6n) is 0. It starts counting when the start bit has been detected. The counter stops operation after one frame has been received, until the next start bit is detected. Remark n = 0, 1 326 User's Manual U17555EJ3V0UD www..com CHAPTER 13 SERIAL INTERFACES UART60 AND UART61 Figure 13-32. Configuration of Baud Rate Generator POWER6n fPRS fPRS/2 fPRS/22 fPRS/23 fPRS/24 fPRS/25 fPRS/26 fPRS/27 fPRS/28 fPRS/29 fPRS/210 8-bit timer/ event counter 50 output Baud rate generator POWER6n, TXE6n (or RXE6n) Selector fXCLK6 8-bit counter Match detector 1/2 Baud rate CKSR6n: TPS63n to TPS60n BRGC6n: MDL67n to MDL60n Remark POWER6n: Bit 7 of asynchronous serial interface operation mode register 6n (ASIM6n) TXE6n: RXE6n: CKSR6n: BRGC6n: n = 0, 1 Bit 6 of ASIM6n Bit 5 of ASIM6n Clock selection register 6n Baud rate generator control register 6n (2) Generation of serial clock A serial clock can be generated by using clock selection register 6n (CKSR6n) and baud rate generator control register 6n (BRGC6n). Select the clock to be input to the 8-bit counter by using bits 3 to 0 (TPS63n to TPS60n) of CKSR6n. Bits 7 to 0 (MDL67n to MDL60n) of BRGC6n can be used to select the division value of the 8-bit counter. (a) Baud rate The baud rate can be calculated by the following expression. * Baud rate = fXCLK6 2xk [bps] fXCLK6: Frequency of base clock selected by TPS63n to TPS60n bits of CKSR6n register (b) Error of baud rate The baud rate error can be calculated by the following expression. * Error (%) = Actual baud rate (baud rate with error) Desired baud rate (correct baud rate) - 1 x 100 [%] User's Manual U17555EJ3V0UD 327 www..com CHAPTER 13 SERIAL INTERFACES UART60 AND UART61 Cautions 1. Keep the baud rate error during transmission to within the permissible error range at the reception destination. 2. Make sure that the baud rate error during reception satisfies the range shown in (4) Permissible baud rate range during reception. Example: Frequency of base clock = 10 MHz = 10,000,000 Hz Set value of MDL67n to MDL60n bits of BRGC6 register = 00100001B (k = 33) Target baud rate = 153600 bps Baud rate = 10 M/(2 x 33) = 10000000/(2 x 33) = 151,515 [bps] Error = (151515/153600 - 1) x 100 = -1.357 [%] (3) Example of setting baud rate Table 13-4. Set Data of Baud Rate Generator Baud Rate [bps] TPS63n, TPS60n fPRS = 5.0 MHz k Calculated Value fPRS = 10.0 MHz ERR [%] 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0 0.16 0.16 -1.36 -1.36 1.73 0 0 TPS63n, TPS60n fPRS = 20.0 MHz ERR [%] 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0 0.16 0.16 0.16 0.94 -1.36 0 0 TPS63n, TPS60n k Calculated Value k Calculated Value ERR [%] 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0 0.16 0.16 0.16 -0.22 -1.36 0 0 300 600 1200 2400 4800 9600 19200 24000 31250 38400 48000 76800 115200 153600 312500 7H 6H 5H 4H 3H 2H 1H 3H 4H 0H 2H 0H 1H 1H 0H 0H 65 65 65 65 65 65 65 13 5 65 13 33 11 8 8 4 301 601 1202 2404 4808 9615 19231 24038 31250 38462 48077 75758 113636 156250 312500 625000 8H 7H 6H 5H 4H 3H 2H 4H 5H 1H 3H 0H 0H 0H 1H 1H 65 65 65 65 65 65 65 13 5 65 13 65 43 33 8 4 301 601 1202 2404 4808 9615 19231 24038 31250 38462 48077 76923 116279 151515 312500 625000 9H 8H 7H 6H 5H 4H 3H 5H 6H 2H 4H 1H 0H 1H 2H 2H 65 65 65 65 65 65 65 13 5 65 13 65 87 33 8 4 301 601 1202 2404 4808 9615 19231 24038 31250 38462 48077 76923 114943 151515 312500 625000 625000 Remark TPS63n to TPS60n: k Bits 3 to 0 of clock selection register 6n (CKSR6n) (setting of base clock (fXCLK6)) Value set by MDL67n to MDL60n bits of baud rate generator control register 6n (BRGC6n) (k = 4, 5, 6, ..., 255) Peripheral hardware clock frequency Baud rate error 328 User's Manual U17555EJ3V0UD www..com CHAPTER 13 SERIAL INTERFACES UART60 AND UART61 (4) Permissible baud rate range during reception The permissible error from the baud rate at the transmission destination during reception is shown below. Caution Make sure that the baud rate error during reception is within the permissible error range, by using the calculation expression shown below. Figure 13-33. Permissible Baud Rate Range During Reception Latch timing Data frame lengtz of UART60 and UART61 Start bit Bit 0 FL Bit 1 Bit 7 Parity bit Stop bit 1 data frame (11 x FL) Minimum permissible data frame length Start bit Bit 0 Bit 1 Bit 7 Parity bit Stop bit FLmin Maximum permissible data frame length Start bit Bit 0 Bit 1 Bit 7 Parity bit Stop bit FLmax As shown in Figure 13-33, the latch timing of the receive data is determined by the counter set by baud rate generator control register 6n (BRGC6n) after the start bit has been detected. If the last data (stop bit) meets this latch timing, the data can be correctly received. Assuming that 11-bit data is received, the theoretical values can be calculated as follows. FL = (Brate)-1 Brate: Baud rate of UART60 and UART61 k: FL: Set value of BRGC6n 1-bit data length Margin of latch timing: 2 clocks Remark n = 0, 1 User's Manual U17555EJ3V0UD 329 www..com CHAPTER 13 SERIAL INTERFACES UART60 AND UART61 Minimum permissible data frame length: FLmin = 11 x FL - k-2 2k x FL = 21k + 2 2k FL Therefore, the maximum receivable baud rate at the transmission destination is as follows. 22k BRmax = (FLmin/11)-1 = Brate 21k + 2 Similarly, the maximum permissible data frame length can be calculated as follows. 10 11 FLmax = 21k - 2 20k x FLmax = 11 x FL - k+2 2xk x FL = 21k - 2 2xk FL FL x 11 Therefore, the minimum receivable baud rate at the transmission destination is as follows. BRmin = (FLmax/11)-1 = 20k 21k - 2 Brate The permissible baud rate error between UART60 and UART61 and the transmission destination can be calculated from the above minimum and maximum baud rate expressions, as follows. Table 13-5. Maximum/Minimum Permissible Baud Rate Error Division Ratio (k) Maximum Permissible Baud Rate Error +2.33% +3.53% +4.26% +4.56% +4.66% +4.72% Minimum Permissible Baud Rate Error -2.44% -3.61% -4.31% -4.58% -4.67% -4.73% 4 8 20 50 100 255 Remarks 1. The permissible error of reception depends on the number of bits in one frame, input clock frequency, and division ratio (k). The higher the input clock frequency and the higher the division ratio (k), the higher the permissible error. 2. 3. k: Set value of BRGC6n n = 0, 1 330 User's Manual U17555EJ3V0UD www..com CHAPTER 13 SERIAL INTERFACES UART60 AND UART61 (5) Data frame length during continuous transmission When data is continuously transmitted, the data frame length from a stop bit to the next start bit is extended by two clocks of base clock from the normal value. However, the result of communication is not affected because the timing is initialized on the reception side when the start bit is detected. Figure 13-34. Data Frame Length During Continuous Transmission 1 data frame Start bit of second byte Bit 7 FL Parity bit FL Stop bit FLstp Start bit FL Bit 0 FL Start bit FL Bit 0 FL Bit 1 FL Where the 1-bit data length is FL, the stop bit length is FLstp, and base clock frequency is fXCLK6, the following expression is satisfied. FLstp = FL + 2/fXCLK6 Therefore, the data frame length during continuous transmission is: Data frame length = 11 x FL + 2/fXCLK6 User's Manual U17555EJ3V0UD 331 www..com CHAPTER 14 SERIAL INTERFACE CSI10 The 78K0/FC2 incorporate serial interface CSI10. 14.1 Functions of Serial Interface CSI10 Serial interface CSI10 has the following two modes. * Operation stop mode * 3-wire serial I/O mode (1) Operation stop mode This mode is used when serial communication is not performed and can enable a reduction in the power consumption. For details, see 14.4.1 Operation stop mode. (2) 3-wire serial I/O mode (MSB/LSB-first selectable) This mode is used to communicate 8-bit data using three lines: a serial clock line (SCK10) and two serial data lines (SI10 and SO10). The processing time of data communication can be shortened in the 3-wire serial I/O mode because transmission and reception can be simultaneously executed. In addition, whether 8-bit data is communicated with the MSB or LSB first can be specified, so this interface can be connected to any device. The 3-wire serial I/O mode is used for connecting peripheral ICs and display controllers with a clocked serial interface. For details, see 14.4.2 3-wire serial I/O mode. 332 User's Manual U17555EJ3V0UD www..com CHAPTER 14 SERIAL INTERFACE CSI10 14.2 Configuration of Serial Interface CSI10 Serial interface CSI10 includes the following hardware. Item Controller Transmit controller Clock start/stop controller & clock phase controller Registers Transmit buffer register 10 (SOTB10) Serial I/O shift register 10 (SIO10) Control registers Serial operation mode register 10 (CSIM10) Serial clock selection register 10 (CSIC10) Port mode register 1 (PM1) Port register 1 (P1) Table 14-1. Configuration of Serial Interface CSI10 Configuration Figure 14-1. Block Diagram of Serial Interface CSI10 8 SI10/P11/RXD61 Serial I/O shift register 10 (SIO10) Internal bus 8 Transmit buffer register 10 (SOTB10) Output selector (a) SO10/P12 Transmit data controller Output latch Output latch (P12) PM12 Transmit controller fPRS/2 fPRS/22 fPRS/23 fPRS/24 fPRS/25 fPRS/26 fPRS/27 SCK10/P10/TxD61 Selector Clock start/stop controller & clock phase controller INTCSI10 Baud rate generator Output latch (P10) PM10 Remark (a): SO10 output User's Manual U17555EJ3V0UD 333 www..com CHAPTER 14 SERIAL INTERFACE CSI10 (1) Transmit buffer register 10 (SOTB10) This register sets the transmit data. Transmission/reception is started by writing data to SOTB10 when bit 7 (CSIE10) and bit 6 (TRMD10) of serial operation mode register 10 (CSIM10) is 1. The data written to SOTB10 is converted from parallel data into serial data by serial I/O shift register 10, and output to the serial output pin (SO10). SOTB10 can be written or read by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Caution Do not access SOTB10 when CSOT10 = 1 (during serial communication). (2) Serial I/O shift register 10 (SIO10) This is an 8-bit register that converts data from parallel data into serial data and vice versa. This register can be read by an 8-bit memory manipulation instruction. Reception is started by reading data from SIO10 if bit 6 (TRMD10) of serial operation mode register 10 (CSIM10) is 0. During reception, the data is read from the serial input pin (SI10) to SIO10. Reset signal generation clears this register to 00H. Caution Do not access SIO10 when CSOT10 = 1 (during serial communication). 334 User's Manual U17555EJ3V0UD www..com CHAPTER 14 SERIAL INTERFACE CSI10 14.3 Registers Controlling Serial Interface CSI10 Serial interface CSI10 is controlled by the following four registers. * Serial operation mode register 10 (CSIM10) * Serial clock selection register 10 (CSIC10) * Port mode register 1 (PM1) * Port register 1 (P1) (1) Serial operation mode register 10 (CSIM10) CSIM10 is used to select the operation mode and enable or disable operation. CSIM10 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 14-2. Format of Serial Operation Mode Register 10 (CSIM10) Address: FF80H After reset: 00H R/W Symbol CSIM10 <7> CSIE10 CSIE10 0 1 TRMD10 0 Note 5 Note 4 Note 1 6 TRMD10 5 0 4 DIR10 3 0 2 0 1 0 0 CSOT10 Operation control in 3-wire serial I/O mode Disables operation Enables operation Transmit/receive mode control Receive mode (transmission disabled). Transmit/receive mode Note 2 and asynchronously resets the internal circuit Note 3 . 1 DIR10 0 1 CSOT10 0 1 Note 6 First bit specification MSB LSB Communication status flag Communication is stopped. Communication is in progress. Notes 1. Bit 0 is a read-only bit. To use P10/SCK10/TXD61 and P12/SO10 as general-purpose ports, set CSIM10 in the default status (00H). Bit 0 (CSOT10) of CSIM10 and serial I/O shift register 10 (SIO10) are reset. Do not rewrite TRMD10 when CSOT10 = 1 (during serial communication). The SO10 output (see (a) in Figure 14-1) is fixed to the low level when TRMD10 is 0. Reception is started when data is read from SIO10. Do not rewrite DIR10 when CSOT10 = 1 (during serial communication). Caution Be sure to clear bit 5 to 0. User's Manual U17555EJ3V0UD 335 www..com CHAPTER 14 SERIAL INTERFACE CSI10 (2) Serial clock selection register 10 (CSIC10) This register specifies the timing of the data transmission/reception and sets the serial clock. CSIC10 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 14-3. Format of Serial Clock Selection Register 10 (CSIC10) Address: FF81H After reset: 00H R/W Symbol CSIC10 7 0 6 0 5 0 4 CKP10 3 DAP10 2 CKS102 1 CKS101 0 CKS100 CKP10 0 DAP10 0 Specification of data transmission/reception timing Type 1 SCK10 SO10 SI10 input timing D7 D6 D5 D4 D3 D2 D1 D0 0 1 SCK10 SO10 SI10 input timing D7 D6 D5 D4 D3 D2 D1 D0 2 1 0 SCK10 SO10 SI10 input timing D7 D6 D5 D4 D3 D2 D1 D0 3 1 1 SCK10 SO10 SI10 input timing D7 D6 D5 D4 D3 D2 D1 D0 4 CKS102 CKS101 CKS100 CSI10 serial clock selection fPRS = 4 MHz fPRS = 5 MHz 2.5 MHz 1.25 MHz 625 kHz 312.5 kHz fPRS = 10 MHz 5 MHz 2.5 MHz 1.25 MHz 625 kHz fPRS = 20 MHz 10 MHz 5 MHz 2.5 MHz 1.25 MHz 625 kHz Mode 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 fPRS/2 fPRS/2 fPRS/2 fPRS/2 fPRS/2 fPRS/2 fPRS/2 2 2 MHz 1 MHz 500 kHz 250 kHz 125 kHz 62.5 kHz Master mode 3 4 5 156.25 kHz 312.5 kHz 78.13 kHz 6 156.25 kHz 312.5 kHz 156.25 kHz Slave mode 7 31.25 kHz 39.06 kHz 78.13 kHz External clock input to SCK10 Cautions 1. Do not write to CSIC10 while CSIE10 = 1 (operation enabled). 336 User's Manual U17555EJ3V0UD www..com CHAPTER 14 SERIAL INTERFACE CSI10 (3) Port mode registers 1 (PM1) These registers set port 1 input/output in 1-bit units. When using P10/SCK10 as the clock output pins of the serial interface, clear PM10 to 0, and the output latches of P10 to 1. When using P12/SO10 as the data output pins of the serial interface, clear PM12, P12 to 0. When using P10/SCK10/TxD61 as the clock input pins of the serial interface, P11/SI10/RxD61 as the data input pins, set PM10 and M11 to 1. At this time, the output latches of P10 and P11 may be 0 or 1. PM1 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets these registers to FFH. Figure 14-4. Format of Port Mode Register 1 (PM1) Address: FF21H After reset: FFH R/W Symbol PM1 7 PM17 6 PM16 5 PM15 4 PM14 3 PM13 2 PM12 1 PM11 0 PM10 PM10 0 1 P1n pin I/O mode selection (n = 0 to 7) Output mode (Output buffer on) Input mode (Output buffer off) User's Manual U17555EJ3V0UD 337 www..com CHAPTER 14 SERIAL INTERFACE CSI10 14.4 Operation of Serial Interface CSI10 Serial interface CSI10 can be used in the following two modes. * Operation stop mode * 3-wire serial I/O mode 14.4.1 Operation stop mode Serial communication is not executed in this mode. Therefore, the power consumption can be reduced. In addition, the P10/SCK10/TXD61, P11/SI10/RXD61 and P12/SO10 pins can be used as ordinary I/O port pins in this mode. (1) Register used The operation stop mode is set by serial operation mode register 10 (CSIM10). To set the operation stop mode, clear bit 7 (CSIE10) of CSIM10 to 0. (a) Serial operation mode register 10 (CSIM10) CSIM10 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears CSIM10 to 00H. * Serial operation mode register 10 (CSIM10) Address: FF80H After reset: 00H R/W Symbol CSIM10 <7> CSIE10 6 TRMD10 5 0 4 DIR10 3 0 2 0 1 0 0 CSOT10 CSIE10 0 Disables operation Note 1 Operation control in 3-wire serial I/O mode and asynchronously resets the internal circuit Note 2 . Notes 1. 2. To use P10/SCK10/TXD61 and P12/SO10 as general-purpose ports, set CSIM10 in the default status (00H). Bit 0 (CSOT10) of CSIM10 and serial I/O shift register 10 (SIO10) are reset. 338 User's Manual U17555EJ3V0UD www..com CHAPTER 14 SERIAL INTERFACE CSI10 14.4.2 3-wire serial I/O mode The 3-wire serial I/O mode is used for connecting peripheral ICs and display controllers with a clocked serial interface. In this mode, communication is executed by using three lines: the serial clock (SCK10), serial output (SO10), and serial input (SI10) lines. (1) Registers used * Serial operation mode register 10 (CSIM10) * Serial clock selection register 10 (CSIC10) * Port mode register 1 (PM1) * Port register 1 (P1) The basic procedure of setting an operation in the 3-wire serial I/O mode is as follows. <1> Set the CSIC10 register (see Figures 14-3). <2> Set bits 0 and 4 to 6 (CSOT10, DIR10, and TRMD10) of the CSIM10 register (see Figures 14-2). <3> Set bit 7 (CSIE10) of the CSIM10 register to 1. Transmission/reception is enabled. <4> Write data to transmit buffer register 10 (SOTB10). Data transmission/reception is started. Read data from serial I/O shift register 10 (SIO10). Data reception is started. Caution Take relationship with the other party of communication when setting the port mode register and port register. User's Manual U17555EJ3V0UD 339 www..com CHAPTER 14 SERIAL INTERFACE CSI10 The relationship between the register settings and pins is shown below. Table 14-2. Relationship Between Register Settings and Pins (a) Serial interface CSI10 CSIE10 TRMD10 PM11 P11 PM12 P12 PM10 P10 CSI10 Operation Pin Function SI10/RxD61/ SO10/P12 SCK10/TxD61/ P11 0 x x Note 1 P10 P12 TxD61/ P10 P12 Note 2 x Note 1 x Note 1 x Note 1 x Note 1 x Note 1 Stop RxD61/ P11 1 0 1 Note 1 x Note 1 x Note 1 x Note 1 1 x Slave reception Note 3 SI10 SCK10 (input) Note 3 1 1 x x 0 0 1 x Slave transmission Note 3 RxD61/ P11 SI10 Note 3 SO10 SCK10 (input) Note 3 1 1 1 x 0 0 1 x Slave transmission/ reception SO10 SCK10 (input) Note 3 1 0 1 Note 1 x Note 1 x Note 1 x Note 1 0 1 Master reception SI10 P12 SCK10 (output) 1 1 x x 0 0 0 1 Master transmission RxD61/ P11 SI10 SO10 SCK10 (output) 1 1 1 x 0 0 0 1 Master transmission/ reception SO10 SCK10 (output) Notes 1. 2. 3. Remark Can be set as port function. To use P10/SCK10/TxD61 as port pins, clear CKP10 to 0. To use the slave mode, set CKS102, CKS101, and CKS100 to 1, 1, 1. x: CSIE10: TRMD10: CKP10: PM1x: P1x: don't care Bit 7 of serial operation mode register 10 (CSIM10) Bit 6 of CSIM10 Bit 4 of serial clock selection register 10 (CSIC10) Port mode register Port output latch CKS102, CKS101, CKS100: Bits 2 to 0 of CSIC10 340 User's Manual U17555EJ3V0UD www..com CHAPTER 14 SERIAL INTERFACE CSI10 (2) Communication operation In the 3-wire serial I/O mode, data is transmitted or received in 8-bit units. Each bit of the data is transmitted or received in synchronization with the serial clock. Data can be transmitted or received if bit 6 (TRMD10) of serial operation mode register 10 (CSIM10) is 1. Transmission/reception is started when a value is written to transmit buffer register 10 (SOTB10). In addition, data can be received when bit 6 (TRMD10) of serial operation mode register 10 (CSIM10) is 0. Reception is started when data is read from serial I/O shift register 10 (SIO10). After communication has been started, bit 0 (CSOT10) of CSIM10 is set to 1. When communication of 8-bit data has been completed, a communication completion interrupt request flag (CSIIF10) is set, and CSOT10 is cleared to 0. Then the next communication is enabled. Caution Do not access the control register and data register when CSOT10 = 1 (during serial communication). Figure 14-5. Timing in 3-Wire Serial I/O Mode (1/2) (1) Transmission/reception timing (Type 1; TRMD10 = 1, DIR10 = 0, CKP10 = 0, DAP10 = 0) SCK10 Read/write trigger SOTB10 55H (communication data) SIO10 ABH 56H ADH 5AH B5H 6AH D5H AAH CSOT10 INTCSI10 CSIIF10 SI1n (receive AAH) SO10 55H is written to SOTB10 User's Manual U17555EJ3V0UD 341 www..com CHAPTER 14 SERIAL INTERFACE CSI10 Figure 14-5. Timing in 3-Wire Serial I/O Mode (2/2) (2) Transmission/reception timing (Type 2; TRMD10 = 1, DIR10 = 0, CKP10 = 0, DAP10 = 1) SCK10 Read/write trigger SOTB10 55H (communication data) SIO10 ABH 56H ADH 5AH B5H 6AH D5H AAH CSOT10 INTCSI10 CSIIF10 SI10input AAH) SO10 55H is written to SOTB10. 342 User's Manual U17555EJ3V0UD www..com CHAPTER 14 SERIAL INTERFACE CSI10 Figure 14-6. Timing of Clock/Data Phase (a) Type 1; CKP10 = 0, DAP10 = 0, DIR10 = 0 SCK10 SI10 capture SO10 Writing to SOTB10 or reading from SIO10 CSIIF10 CSOT10 D7 D6 D5 D4 D3 D2 D1 D0 (b) Type 2; CKP10 = 0, DAP10 = 1, DIR10 = 0 SCK10 SI10 capture SO10 Writing to SOTB10 or reading from SIO10 CSIIF10 CSOT10 D7 D6 D5 D4 D3 D2 D1 D0 (c) Type 3; CKP10 = 1, DAP10 = 0, DIR10 = 0 SCK10 SI10 capture SO10 Writing to SOTB10 or reading from SIO10 CSIIF10 CSOT10 D7 D6 D5 D4 D3 D2 D1 D0 (d) Type 4; CKP10 = 1, DAP10 = 1, DIR10 = 0 SCK10 SI10 capture SO10 Writing to SOTB10 or reading from SIO10 CSIIF10 CSOT10 D7 D6 D5 D4 D3 D2 D1 D0 Remark The above figure illustrates a communication operation where data is transmitted with the MSB first. User's Manual U17555EJ3V0UD 343 www..com CHAPTER 14 SERIAL INTERFACE CSI10 SCK10 Writing to SOTB10 or reading from SIO10 SOTB10 SIO10 Output latch SO10 First bit 2nd bit (b) Type 3: CKP10 = 1, DAP10 = 0 SCK10 Writing to SOTB10 or reading from SIO10 SOTB10 SIO10 Output latch SO10 First bit 2nd bit The first bit is directly latched by the SOTB10 register to the output latch at the falling (or rising) edge of SCK10, and output from the SO10 pin via an output selector. Then, the value of the SOTB10 register is transferred to the SIO10 register at the next rising (or falling) edge of SCK10, and shifted one bit. At the same time, the first bit of the receive data is stored in the SIO10 register via the SI10 pin. The second and subsequent bits are latched by the SIO10 register to the output latch at the next falling (or rising) edge of SCK10, and the data is output from the SO10 pin. 344 User's Manual U17555EJ3V0UD www..com CHAPTER 14 SERIAL INTERFACE CSI10 Figure 14-7. Output Operation of First Bit (2/2) (c) Type 2: CKP10 = 0, DAP10 = 1 SCK10 Writing to SOTB10 or reading from SIO10 SOTB10 SIO10 Output latch SO10 First bit 2nd bit 3rd bit (d) Type 4: CKP10 = 1, DAP10 = 1 SCK10 Writing to SOTB10 or reading from SIO10 SOTB10 SIO10 Output latch SO10 First bit 2nd bit 3rd bit The first bit is directly latched by the SOTB10 register at the falling edge of the write signal of the SOTB10 register or the read signal of the SIO10 register, and output from the SO10 pin via an output selector. Then, the value of the SOTB10 register is transferred to the SIO10 register at the next falling (or rising) edge of SCK10, and shifted one bit. At the same time, the first bit of the receive data is stored in the SIO10 register via the SI10 pin. The second and subsequent bits are latched by the SIO10 register to the output latch at the next rising (or falling) edge of SCK10, and the data is output from the SO10 pin. User's Manual U17555EJ3V0UD 345 www..com CHAPTER 14 SERIAL INTERFACE CSI10 SCK10 Writing to SOTB10 or reading from SIO10 SOTB10 SIO10 Output latch SO10 Last bit ( Next request is issued.) (b) Type 3: CKP10 = 1, DAP10 = 0 SCK10 Writing to SOTB10 or reading from SIO10 SOTB10 SIO10 Output latch SO10 Last bit ( Next request is issued.) 346 User's Manual U17555EJ3V0UD www..com CHAPTER 14 SERIAL INTERFACE CSI10 Figure 14-8. Output Value of SO10 Pin (Last Bit) (2/2) (c) Type 2: CKP10 = 0, DAP10 = 1 SCK10 Writing to SOTB10 or reading from SIO10 SOTB10 SIO10 Output latch SO10 Last bit ( Next request is issued.) (d) Type 4: CKP10 = 1, DAP10 = 1 SCK10 Writing to SOTB10 or reading from SIO10 SOTB10 SIO10 Output latch SO10 Last bit ( Next request is issued.) User's Manual U17555EJ3V0UD 347 www..com CHAPTER 14 SERIAL INTERFACE CSI10 TRMD10 TRMD10 = 0 TRMD10 = 1 Note DAP10 - DAP10 = 0 DIR10 - - DIR10 = 0 DIR10 = 1 SO10 Output Outputs low level Note 2 Note 1 Value of SO10 latch (low-level output) DAP10 = 1 Value of bit 7 of SOTB10 Value of bit 0 of SOTB10 Notes 1. 2. The actual output of the SO10/P12 pin is determined according to PM12 and P12, as well as the SO10 output. Status after reset Caution If a value is written to TRMD10, DAP10, and DIR10, the output value of SO10 changes. 348 User's Manual U17555EJ3V0UD www..com CHAPTER 15 CAN CONTROLLER 15.1 Outline Description This product features an on-chip 1-channel CAN (Controller Area Network) controller that complies with CAN protocol as standardized in ISO 11898. 15.1.1 Features - Compliant with ISO 11898 and tested according to ISO/DIS 16845 (CAN conformance test) - Standard frame and extended frame transmission/reception enabled - Transfer rate: 1 Mbps max. (CAN clock input 8 MHz) - 16 message buffers/1 channel - Receive/transmit history list function - Automatic block transmission function - Multi-buffer receive block function - Mask setting of four patterns is possible for each channel User's Manual U17555EJ3V0UD 349 www..com CHAPTER 15 CAN CONTROLLER 15.1.2 Overview of functions Table 15-1 presents an overview of the CAN controller functions. Table 15-1. Overview of Functions Function Protocol Baud rate Data storage Number of messages Details CAN protocol ISO 11898 (standard and extended frame transmission/reception) Maximum 1 Mbps (CAN clock input 8 MHz) Storing messages in the CAN RAM - 16 message buffers/1 channel - Each message buffer can be set to be either a transmit message buffer or a receive message buffer. Message reception - Unique ID can be set to each message buffer. - Mask setting of four patterns is possible for each channel. - A receive completion interrupt is generated each time a message is received and stored in a message buffer. - Two or more receive message buffers can be used as a FIFO receive buffer (multi-buffer receive block function). - Receive history list function Message transmission - Unique ID can be set to each message buffer. - Transmit completion interrupt for each message buffer - Message buffer number 0 to 7 specified as the transmit message buffer can be used for automatic block transfer. Message transmission interval is programmable (automatic block transmission function (hereafter referred to as "ABT")). - Transmission history list function Remote frame processing Time stamp function Remote frame processing by transmit message buffer - The time stamp function can be set for a message reception when a 16-bit timer is used in combination. Time stamp capture trigger can be selected (SOF or EOF in a CAN message frame can be detected.). Diagnostic function - Readable error counters - "Valid protocol operation flag" for verification of bus connections - Receive-only mode - Single-shot mode - CAN protocol error type decoding - Self-test mode Forced release from bus-off state - Forced release from bus-off (by ignoring timing constraint) possible by software. - No automatic release from bus-off (software must re-enable). Power save mode - CAN sleep mode (can be woken up by CAN bus) - CAN stop mode (cannot be woken up by CAN bus) 350 User's Manual U17555EJ3V0UD www..com CHAPTER 15 CAN CONTROLLER 15.1.3 Configuration The CAN controller is composed of the following four blocks. (1) NPB interface This functional block provides an NPB (NEC peripheral I/O bus) interface and means of transmitting and receiving signals between the CAN module and the host CPU. (2) MCM (Message Control Module) This functional block controls access to the CAN protocol layer and to the CAN RAM within the CAN module. (3) CAN protocol layer This functional block is involved in the operation of the CAN protocol and its related settings. (4) CAN RAM This is the CAN memory functional block, which is used to store message IDs, message data, etc. Figure 15-1. Block Diagram of CAN Module CPU Interrupt request INTTRX0 INTREC0 INTERR0 INTWUP0 NPB (NEC Peripheral I/O Bus) CAN module CAN bus NPB interface MCM (Message Control Module) CAN Protocol Layer CTXD CRXD CAN transceiver CAN_H0 CAN_L0 CAN RAM Message buffer 0 Message buffer 1 Message buffer 2 Message buffer 3 Message buffer 15 ... C0MASK1 C0MASK2 C0MASK3 C0MASK4 User's Manual U17555EJ3V0UD 351 www..com CHAPTER 15 CAN CONTROLLER 15.2 CAN Protocol CAN (Controller Area Network) is a high-speed multiplex communication protocol for real-time communication in automotive applications (class C). specifications. The CAN specification is generally divided into two layers: a physical layer and a data link layer. In turn, the data link layer includes logical link and medium access control. The composition of these layers is illustrated below. Figure 15-2. Composition of Layers CAN is prescribed by ISO 11898. For details, refer to the ISO 11898 Higher Data link layerNote * Logical link control (LLC) * Medium access control (MAC) * Acceptance filtering * Overload report * Recovery management * Data capsuled/not capsuled * Frame coding (stuffing/not stuffing) * Medium access management * Error detection * Error report * Acknowledgement * Seriated/not seriated Prescription of signal level and bit description Lower Physical layer Note CAN controller specification 15.2.1 Frame format (1) Standard format frame - The standard format frame uses 11-bit identifiers, which means that it can handle up to 2048 messages. (2) Extended format frame - The extended format frame uses 29-bit (11 bits + 18 bits) identifiers which increase the number of messages that can be handled to 2048 x 218 messages. - Extended format frame is set when "recessive level" (CMOS level equals "1") is set for both the SRR and IDE bits in the arbitration field. 352 User's Manual U17555EJ3V0UD www..com CHAPTER 15 CAN CONTROLLER 15.2.2 Frame types The following four types of frames are used in the CAN protocol. Table 15-2. Frame Types Frame Type Data frame Remote frame Error frame Overload frame Frame used to transmit data Frame used to request a data frame Frame used to report error detection Frame used to delay the next data frame or remote frame Description (1) Bus value The bus values are divided into dominant and recessive. - Dominant level is indicated by logical 0. - Recessive level is indicated by logical 1. - When a dominant level and a recessive level are transmitted simultaneously, the bus value becomes dominant level. 15.2.3 Data frame and remote frame (1) Data frame A data frame is composed of seven fields. Figure 15-3. Data Frame Data frame R D <1> <2> <3> <4> <5> <6> <7> <8> Interframe space End of frame (EOF) ACK field CRC field Data field Control field Arbitration field Start of frame (SOF) Remark D: Dominant = 0 R: Recessive = 1 User's Manual U17555EJ3V0UD 353 www..com CHAPTER 15 CAN CONTROLLER (2) Remote frame A remote frame is composed of six fields. Figure 15-4. Remote Frame Remote frame R D <1> <2> <3> <5> <6> <7> <8> Interframe space End of frame (EOF) ACK field CRC field Control field Arbitration field Start of frame (SOF) Remarks 1. The data field is not transferred even if the control field's data length code is not "0000B". 2. D: Dominant = 0 R: Recessive = 1 (3) Description of fields <1> Start of frame (SOF) The start of frame field is located at the start of a data frame or remote frame. Figure 15-5. Start of Frame (SOF) (Interframe space or bus idle) R D Start of frame (Arbitration field) 1 bit Remark D: Dominant = 0 R: Recessive = 1 * If dominant level is detected in the bus idle state, a hard-synchronization is performed (the current TQ is assigned to be the SYNC segment). * If dominant level is sampled at the sample point following such a hard-synchronization, the bit is assigned to be a SOF. If recessive level is detected, the protocol layer returns to the bus idle state and regards the preceding dominant pulse as a disturbance only. No error frame is generated in such case. 354 User's Manual U17555EJ3V0UD www..com CHAPTER 15 CAN CONTROLLER <2> Arbitration field The arbitration field is used to set the priority, data frame/remote frame, and frame format. Figure 15-6. Arbitration Field (in Standard Format Mode) Arbitration field R D Identifier RTR (Control field) IDE (r1) (1 bit) r0 ID28 * * * * * * * * * * * * * * * * * * * * ID18 (11 bits) (1 bit) Cautions 1. ID28 to ID18 are identifiers. 2. An identifier is transmitted MSB first. Remark D: Dominant = 0 R: Recessive = 1 Figure 15-7. Arbitration Field (in Extended Format Mode) Arbitration field R D Identifier SRR IDE Identifier RTR (Control field) r1 r0 ID28 * * * * * * * * * * * * * * ID18 ID17 * * * * * * * * * * * * * * * * * ID0 (11 bits) (1 bit) (1 bit) (18 bits) (1 bit) Cautions 1. ID28 to ID18 are identifiers. 2. An identifier is transmitted MSB first. Remark D: Dominant = 0 R: Recessive = 1 Table 15-3. RTR Frame Settings Frame Type Data frame Remote frame 0 (D) 1 (R) RTR Bit Table 15-4. Frame Format Setting (IDE Bit) and Number of Identifier (ID) Bits Frame Format Standard format mode Extended format mode SRR Bit None 1 (R) IDE Bit 0 (D) 1 (R) Number. of Bits 11 bits 29 bits User's Manual U17555EJ3V0UD 355 www..com CHAPTER 15 CAN CONTROLLER <3> Control field The control field sets "N" as the number of data bytes in the data field (N = 0 to 8). Figure 15-8. Control Field (Arbitration field) R D RTR r1 (IDE) r0 Control field (Data field) DLC3 DLC2 DLC1 DLC0 Remark D: Dominant = 0 R: Recessive = 1 In a standard format frame, the control field's IDE bit is the same as the r1 bit. Table 15-5. Data Length Setting Data Length Code DLC3 0 0 0 0 0 0 0 0 1 DLC2 0 0 0 0 1 1 1 1 0 DLC1 0 0 1 1 0 0 1 1 0 DLC0 0 1 0 1 0 1 0 1 0 0 bytes 1 byte 2 bytes 3 bytes 4 bytes 5 bytes 6 bytes 7 bytes 8 bytes 8 bytes regardless of the value of DLC3 to DLC0 Data Byte Count Other than above Caution In the remote frame, there is no data field even if the data length code is not 0000B. 356 User's Manual U17555EJ3V0UD www..com CHAPTER 15 CAN CONTROLLER <4> Data field The data field contains the amount of data (byte units) set by the control field. Up to 8 units of data can be set. Figure 15-9. Data Field (Control field) R D Data0 (8 bits) Data field (CRC field) MSB LSB MSB Data7 (8 bits) LSB Remark D: Dominant = 0 R: Recessive = 1 <5> CRC field The CRC field is a 16-bit field that is used to check for errors in transmit data. Figure 15-10. CRC Field (Data field or control field) R D CRC field (ACK field) CRC sequence CRC delimiter (1 bit) (15 bits) Remark D: Dominant = 0 R: Recessive = 1 - The polynomial P(X) used to generate the 15-bit CRC sequence is expressed as follows. P(X) = X15 + X14 + X10 + X8 + X7 + X4 + X3 + 1 - Transmitting node: Transmits the CRC sequence calculated from the data (before bit stuffing) in the start of frame, arbitration field, control field, and data field. - Receiving node: Compares the CRC sequence calculated using data bits that exclude the stuffing bits in the receive data with the CRC sequence in the CRC field. If the two CRC sequences do not match, the node issues an error frame. User's Manual U17555EJ3V0UD 357 www..com CHAPTER 15 CAN CONTROLLER <6> ACK field The ACK field is used to acknowledge normal reception. Figure 15-11. ACK Field (CRC field) R D ACK field (End of frame) ACK slot (1 bit) ACK delimiter (1 bit) Remark D: Dominant = 0 R: Recessive = 1 - If no CRC error is detected, the receiving node sets the ACK slot to the dominant level. - The transmitting node outputs two recessive-level bits. <7> End of frame (EOF) The end of frame field indicates the end of data frame/remote frame. Figure 15-12. End of Frame (EOF) (ACK field) R D End of frame (Interframe space or overload frame) (7 bits) Remark D: Dominant = 0 R: Recessive = 1 358 User's Manual U17555EJ3V0UD www..com CHAPTER 15 CAN CONTROLLER <8> Interframe space The interframe space is inserted after a data frame, remote frame, error frame, or overload frame to separate one frame from the next. - The bus state differs depending on the error status. (a) Error active node The interframe space consists of a 3-bit intermission field and a bus idle field. Figure 15-13. Interframe Space (Error Active Node) (Frame) R D Interframe space (Frame) Intermission (3 bits) Bus idle (0 to bits) Remarks 1. Bus idle: State in which the bus is not used by any node. 2. D: Dominant = 0 R: Recessive = 1 (b) Error passive node The interframe space consists of an intermission field, a suspend transmission field, and a bus idle field. Figure 15-14. Interframe Space (Error Passive Node) (Frame) R D Interframe space (Frame) Intermission (3 bits) Suspend transmission (8 bits) Bus idle (0 to bits) Remarks 1. Bus idle: State in which the bus is not used by any node. the error passive status. Suspend transmission: Sequence of 8 recessive-level bits transmitted from the node in 2. D: Dominant = 0 R: Recessive = 1 Usually, the intermission field is 3 bits. If the transmitting node detects a dominant level at the third bit of the intermission field, however, it executes transmission. User's Manual U17555EJ3V0UD 359 www..com CHAPTER 15 CAN CONTROLLER - Operation in error status Table 15-6. Operation in Error Status Error Status Error active Error passive Operation A node in this status can transmit immediately after a 3-bit intermission. A node in this status can transmit 8 bits after the intermission. 360 User's Manual U17555EJ3V0UD www..com CHAPTER 15 CAN CONTROLLER 15.2.4 Error frame An error frame is output by a node that has detected an error. Figure 15-15. Error Frame Error frame R D (<4>) <1> 6 bits <2> 0 to 6 bits <3> 8 bits Interframe space or overload frame Error delimiter Error flag2 Error flag1 Error bit (<5>) Remark D: Dominant = 0 R: Recessive = 1 Table 15-7. Definition Error Frame Fields No. <1> Error flag1 Name Bit Count 6 Definition Error active node: Outputs 6 dominant-level bits consecutively. Error passive node: Outputs 6 recessive-level bits consecutively. If another node outputs a dominant level while one node is outputting a passive error flag, the passive error flag is not cleared until the same level is detected 6 bits in a row. <2> Error flag2 0 to 6 Nodes receiving error flag 1 detect bit stuff errors and issues this error flag. <3> Error delimiter 8 Outputs 8 recessive-level bits consecutively. If a dominant level is detected at the 8th bit, an overload frame is transmitted from the next bit. <4> Error bit - The bit at which the error was detected. The error flag is output from the bit next to the error bit. In the case of a CRC error, this bit is output following the ACK delimiter. <5> Interframe space/overload frame - An interframe space or overload frame starts from here.5 User's Manual U17555EJ3V0UD 361 www..com CHAPTER 15 CAN CONTROLLER 15.2.5 Overload frame An overload frame is transmitted under the following conditions. - When the receiving node has not completed the reception operationNote - If a dominant level is detected at the first two bits during intermission - If a dominant level is detected at the last bit (7th bit) of the end of frame or at the last bit (8th bit) of the error delimiter/overload delimiter Note The CAN is internally fast enough to process all received frames not generating overload frames. Figure 15-16. Overload Frame Overload frame R D (<4>) <1> 6 bits <2> 0 to 6 bits <3> 8 bits Interframe space or overload frame Overload delimiter Overload flag Overload flag Frame (<5>) Remark D: Dominant = 0 R: Recessive = 1 Table 15-8. Definition of Overload Frame Fields No <1> <2> Name Overload flag Overload flag from other node Bit Count 6 0 to 6 Definition Outputs 6 dominant-level bits consecutively. The node that received an overload flag in the interframe space outputs an overload flag. <3> Overload delimiter 8 Outputs 8 recessive-level bits consecutively. If a dominant level is detected at the 8th bit, an overload frame is transmitted from the next bit. <4> Frame - Output following an end of frame, error delimiter, or overload delimiter. An interframe space or overload frame starts from here. <5> Interframe space/overload frame - 362 User's Manual U17555EJ3V0UD www..com CHAPTER 15 CAN CONTROLLER 15.3 Functions 15.3.1 Determining bus priority (1) When a node starts transmission: - During bus idle, the node that output data first transmits the data. (2) When more than one node starts transmission: - The node that outputs the dominant level for the longest consecutively from the first bit of the arbitration field acquires the bus priority (if a dominant level and a recessive level are simultaneously transmitted, the dominant level is taken as the bus value). - The transmitting node compares its output arbitration field and the data level on the bus. Table 15-9. Determining Bus Priority Level match Level mismatch Continuous transmission Continuous transmission (3) Priority of data frame and remote frame - When a data frame and a remote frame are on the bus, the data frame has priority because its RTR bit, the last bit in the arbitration field, carries a dominant level. Remark If the extended-format data frame and the standard-format remote frame conflict on the bus (if ID28 to ID18 of both of them are the same), the standard-format remote frames takes priority. 15.3.2 Bit stuffing Bit stuffing is used to establish synchronization by appending 1-bit inverted data if the same level continues for 5 bits, in order to prevent a burst error. Table 15-10. Bit Stuffing Transmission During the transmission of a data frame or remote frame, when the same level continues for 5 bits in the data between the start of frame and the ACK field, 1 inverted-level bit of data is inserted before the following bit. Reception During the reception of a data frame or remote frame, when the same level continues for 5 bits in the data between the start of frame and the ACK field, reception is continued after deleting the next bit. 15.3.3 master. 15.3.4 Multi masters As the bus priority (a node acquiring transmit functions) is determined by the identifier, any node can be the bus Multi cast Although there is one transmitting node, two or more nodes can receive the same data at the same time because the same identifier can be set to two or more nodes. 15.3.5 CAN sleep mode/CAN stop mode function The CAN sleep mode/CAN stop mode function puts the CAN controller in waiting mode to achieve low power consumption. User's Manual U17555EJ3V0UD 363 www..com CHAPTER 15 CAN CONTROLLER The controller is woken up from the CAN sleep mode by bus operation but it is not woken up from the CAN stop mode by bus operation (the CAN stop mode is controlled by CPU access). 15.3.6 Error control function (1) Error types Table 15-11. Error Types Type Description of Error Detection Method Detection Condition Transmission/ Reception Transmitting/ receiving node Bit that outputting data on the bus at the start of frame to end of frame, error frame and overload frame. Stuff error Check the receive data at the stuff bit 6 consecutive bits of the same output level Mismatch of CRC Receiving node CRC field Receiving node Start of frame to CRC sequence Detection State Field/Frame Bit error Comparison of output level and level on the bus Mismatch of levels CRC error Comparison of the CRC sequence generated from the receive data and the received CRC sequence Form error Field/frame check of the fixed format Detection of fixed format violation Receiving node CRC delimiter ACK field End of frame Error frame Overload frame ACK error Check of the ACK slot by the transmitting node Detection of recessive level in ACK slot Transmitting node ACK slot (2) Output timing of error frame Table 15-12. Output Timing of Error Frame Type Bit error, stuff error, form error, ACK error CRC error Output Timing Error frame output is started at the timing of the bit following the detected error. Error frame output is started at the timing of the bit following the ACK delimiter. (3) Processing in case of error The transmission node re-transmits the data frame or remote frame after the error frame (However, it does not re-transmit the frame in the single-shot mode.). 364 User's Manual U17555EJ3V0UD www..com CHAPTER 15 CAN CONTROLLER (4) Error state (a) Types of error states The following three types of error states are defined by the CAN specification. - Error active - Error passive - Bus-off These types of error states are classified by the values of the TEC7 to TEC0 bits (transmission error counter bits) and the REC6 to REC0 bits (reception error counter bits) of the CAN error counter register (C0ERC) as shown in Table 15-13. The present error state is indicated by the CAN module information register (C0INFO). When each error counter value becomes equal to or greater than the error warning level (96), the TECS0 or RECS0 bit of the C0INFO register is set to 1. In this case, the bus state must be tested because it is considered that the bus has a serious fault. An error counter value of 128 or more indicates an error passive state and the TECS1 or RECS1 bit of the C0INFO register is set to 1. - If the value of the transmission error counter is greater than or equal to 256 (actually, the transmission error counter does not indicate a value greater than or equal to 256), the bus-off state is reached and the BOFF bit of the C0INFO register is set to 1. - If only one node is active on the bus at startup (i.e., a particular case such as when the bus is connected only to the local station), ACK is not returned even if data is transmitted. Consequently, retransmission of the error frame and data is repeated. In the error passive state, however, the transmission error counter is not incremented and the bus-off state is not reached. User's Manual U17555EJ3V0UD 365 www..com CHAPTER 15 CAN CONTROLLER Table 15-13. Types of Error States Type Operation Value of Error Counter Error active Transmission Reception Transmission Reception Error passive Transmission Reception 0-95 0-95 96-127 96-127 128-255 128 or more Indication of C0INFO Register TECS1, TECS0 = 00 RECS1, RECS0 = 00 TECS1, TECS0 = 01 RECS1, RECS0 = 01 TECS1, TECS0 = 11 RECS1, RECS0 = 11 - Outputs a passive error flag (6 consecutive recessive-level bits) on detection of the error. - Transmits 8 recessive-level bits, in between transmissions, following an intermission (suspend transmission). Bus-off Transmission 256 or more (not Note indicated) BOFF = 1, TECS1, TECS0 = 11 - Communication is not possible. Messages are not stored when receiving frames, however, the following operations of <1>, <2>, and <3> are done. <1> TSOUT toggles. <2> REC is incremented/decremented. <3> VALID bit is set. - Outputs an active error flag (6 consecutive dominant-level bits) on detection of the error. Operation specific to Given Error State - If the CAN module is entered to the initialization mode and then transition request to any operation mode is made, and when 11 consecutive recessive-level bits are detected 128 times, the error counter is reset to 0 and the error active state can be restored. Note The value of the transmission error counter (TEC) is invalid when the BOFF bit is set to 1. If an error that increments the value of the transmission error counter by +8 while the counter value is in a range of 248 to 255, the counter is not incremented and the bus-off state is assumed. 366 User's Manual U17555EJ3V0UD www..com CHAPTER 15 CAN CONTROLLER (b) Error counter The error counter counts up when an error has occurred, and counts down upon successful transmission State Transmission Error Counter (TEC7 to TEC0) No change Reception Error Counter (REC6 to REC0) +1 (when REPS bit = 0) Receiving node detects an error (except bit error in the active error flag or overload flag). Receiving node detects dominant level following error flag of error frame. Transmitting node transmits an error flag. [As exceptions, the error counter does not change in the following cases.] <1> ACK error is detected in error passive state and dominant level is not detected while the passive error flag is being output. <2> A stuff error is detected in an arbitration field that transmitted a recessive level as a stuff bit, but a dominant level is detected. Bit error detection while active error flag or overload flag is being output (error-active transmitting node) Bit error detection while active error flag or overload flag is being output (error-active receiving node) When the node detects 14 consecutive dominant-level bits from the beginning of the active error flag or overload flag, and then subsequently detects 8 consecutive dominant-level bits. When the node detects 8 consecutive dominant levels after a passive error flag When the transmitting node has completed transmission without error (0 if error counter = 0) When the receiving node has completed reception without error No change +8 (when REPS bit = 0) +8 No change +8 No change No change +8 (when REPS bit = 0) +8 (during transmission) +8 (during reception, when REPS bit = 0) -1 No change - -1 (1 REC6 to REC0 127, when REPS bit = 0) - 0 (REC6 to REC0 = 0, when REPS bit = 0) - Value of 119 to 255 is set (when REPS bit = 1) No change (c) Occurrence of bit error in intermission An overload frame is generated. User's Manual U17555EJ3V0UD 367 www..com CHAPTER 15 CAN CONTROLLER (5) Recovery from bus-off state 368 User's Manual U17555EJ3V0UD www..com CHAPTER 15 CAN CONTROLLER Figure 15-17. Recovery Operation from Bus-off State through Normal Recovery Sequence TEC > FFH error-passive bus-off bus-off-recovery-sequence error-active BOFF bit in C0INFO register OPMODE[2:0] in C0CTRL register (user writings) OPMODE[2:0] in C0CTRL register (user readings) <1> 00H 00H <2> 00H <3> 00H 00H 00H TEC[7:0] in C0ERC 80H TEC[7:0] FFH register FFH < TEC [7:0] 00H 00H TEC[7:0] < 80H REPS, REC[6:0] in C0ERC register 80H REPS, REC[6:0] FFH Undefined 00H REPS, REC[6:0] < 80H (b) Forced recovery operation that skips bus-off recovery sequence The CAN module can be forcibly released from the bus-off state, regardless of the bus state, by skipping the bus-off recovery sequence. Here is the procedure. First, the CAN module requests to enter the initialization mode. For the operation and points to be noted at this time, refer to (a) Recovery operation from bus-off state through normal recovery sequence. Next, the module requests to enter an operation mode. At the same time, the CCERC bit of the C0CTRL register must be set to 1. As a result, the bus-off recovery sequence defined by the CAN protocol ISO 11898 is skipped, and the module immediately enters the operation mode. In this case, the module is connected to the CAN bus after it has monitored 11 consecutive recessive-level bits. For details, refer to the processing in Figure 15-56. Caution This function is not defined by the CAN protocol ISO 11898. When using this function, thoroughly evaluate its effect on the network system. (6) Initializing CAN module error counter register (C0ERC) in initialization mode If it is necessary to initialize the CAN module error counter register (C0ERC) and CAN module information register (C0INFO) for debugging or evaluating a program, they can be initialized to the default value by setting the CCERC bit of the C0CTRL register in the initialization mode. completed, the CCERC bit is automatically cleared to 0. Cautions 1. This function is enabled only in the initialization mode. Even if the CCERC bit is set to 1 in a CAN operation mode, the C0ERC and C0INFO registers are not initialized. 2. The CCERC bit can be set at the same time as the request to enter a CAN operation mode. When initialization has been User's Manual U17555EJ3V0UD 369 www..com CHAPTER 15 CAN CONTROLLER 15.3.7 Baud rate control function (1) Prescaler The CAN controller has a prescaler that divides the clock (fCAN) supplied to CAN. This prescaler generates a Data bit time(DBT) Sync segment Prop segment Phase segment 1 Phase segment 2 Time segment 1(TSEG1) Time segment 2 (TSEG2) Sample point (SPT) Segment Name Time Segment 1 (TSEG1) Time Segment 2 (TSEG2) Settable Range 2TQ-16TQ 1TQ-8TQ Notes on Setting to Confirm to CAN Specification -- IPT of the CAN controller is 0TQ. To conform to the CAN protocol specification, therefore, a length equal to phase segment 1 must be set here. This means that the length of time segment 1 minus 1TQ is the settable upper limit of time segment 2. Resynchronization jump width(SJW) 1TQ-4TQ The length of time segment 1 minus 1TQ or 4 TQ, whichever is smaller. |